JPS55114032A - Limitation system for level variation - Google Patents

Limitation system for level variation

Info

Publication number
JPS55114032A
JPS55114032A JP1963879A JP1963879A JPS55114032A JP S55114032 A JPS55114032 A JP S55114032A JP 1963879 A JP1963879 A JP 1963879A JP 1963879 A JP1963879 A JP 1963879A JP S55114032 A JPS55114032 A JP S55114032A
Authority
JP
Japan
Prior art keywords
output
gain
level variation
circuit
holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1963879A
Other languages
Japanese (ja)
Inventor
Ikuro Moriwaki
Kiichiro Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ANAROGU INTAAFUEESU KK
Original Assignee
ANAROGU INTAAFUEESU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ANAROGU INTAAFUEESU KK filed Critical ANAROGU INTAAFUEESU KK
Priority to JP1963879A priority Critical patent/JPS55114032A/en
Publication of JPS55114032A publication Critical patent/JPS55114032A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To limit the output level variation of a programmable variable gain circuit set to its initial gain by converting the output of the above-mentioned circuit into a digital signal, by holding this signal, and then by controlling the gain of the above-mentioned circuit by the holding output in a direction where its output level variation is limited.
CONSTITUTION: Programmable variable gain circuit VGA set to its initial gain and an A/D converter converting its output into a digital signal are provided; and the output of A/D converter is held by latch circuit LC, etc., and by its holding output, the gain of programmable variable gain circuit VGA is controlled in a direction where its output level variation is limited. As a result, high-speed operation and simple constitution are realized and the accurate gain can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
JP1963879A 1979-02-23 1979-02-23 Limitation system for level variation Pending JPS55114032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1963879A JPS55114032A (en) 1979-02-23 1979-02-23 Limitation system for level variation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1963879A JPS55114032A (en) 1979-02-23 1979-02-23 Limitation system for level variation

Publications (1)

Publication Number Publication Date
JPS55114032A true JPS55114032A (en) 1980-09-03

Family

ID=12004752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1963879A Pending JPS55114032A (en) 1979-02-23 1979-02-23 Limitation system for level variation

Country Status (1)

Country Link
JP (1) JPS55114032A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5034772A (en) * 1973-08-01 1975-04-03
JPS5045506A (en) * 1973-08-27 1975-04-23

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5034772A (en) * 1973-08-01 1975-04-03
JPS5045506A (en) * 1973-08-27 1975-04-23

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