JPS55102043A - Straight line generating circuit - Google Patents

Straight line generating circuit

Info

Publication number
JPS55102043A
JPS55102043A JP823379A JP823379A JPS55102043A JP S55102043 A JPS55102043 A JP S55102043A JP 823379 A JP823379 A JP 823379A JP 823379 A JP823379 A JP 823379A JP S55102043 A JPS55102043 A JP S55102043A
Authority
JP
Japan
Prior art keywords
voltage
signal
integration
straight line
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP823379A
Other languages
Japanese (ja)
Inventor
Kenji Maio
Masahide Okumura
Kanji Ozawa
Akinori Shibayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP823379A priority Critical patent/JPS55102043A/en
Publication of JPS55102043A publication Critical patent/JPS55102043A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Image Generation (AREA)

Abstract

PURPOSE:To enable to generate the voltage wih good linearity, by lowering the start voltage by a given value, setting the objective voltage in excess of a given value and generating the straight line signal between them. CONSTITUTION:The straight line signal generation circuit consists of the operational amplifier A1 constituting the integration circuit, amplifier A2 outputting the input signal with a multiple of 2, comparator 3, control circuit B selectively controlling the switches SW1, SW2, capacitors C0, C1, and resistors R0-R3. In the mode II of hold mode, positive voltage V2 is inputted as the signal S3, and the voltage of the signal S2 is lowered by the voltage DELTAE corresponding to the value of the capacitors C0, C1 and the voltage V2 to set the start voltage. The voltage V0 is given to the input terminal T3 of the comparator A3 and the integration at the integration mode III is set to the potential E2+V1 increasing the potential of the signal S2 by V1. Integration is kept between the start and objective voltage, and the output signal S2 is connected to the deflection circuit system. Thus, the output of the deflection circuit system is changed as the one-dot chain line in Figure S2 to obtain the voltage having good linearity between the potentials E1 and E2.
JP823379A 1979-01-29 1979-01-29 Straight line generating circuit Pending JPS55102043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP823379A JPS55102043A (en) 1979-01-29 1979-01-29 Straight line generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP823379A JPS55102043A (en) 1979-01-29 1979-01-29 Straight line generating circuit

Publications (1)

Publication Number Publication Date
JPS55102043A true JPS55102043A (en) 1980-08-04

Family

ID=11687427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP823379A Pending JPS55102043A (en) 1979-01-29 1979-01-29 Straight line generating circuit

Country Status (1)

Country Link
JP (1) JPS55102043A (en)

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