JPS5498575A - Wiring pattern forming method of master slice lsi - Google Patents

Wiring pattern forming method of master slice lsi

Info

Publication number
JPS5498575A
JPS5498575A JP549378A JP549378A JPS5498575A JP S5498575 A JPS5498575 A JP S5498575A JP 549378 A JP549378 A JP 549378A JP 549378 A JP549378 A JP 549378A JP S5498575 A JPS5498575 A JP S5498575A
Authority
JP
Japan
Prior art keywords
power supply
pattern
logic block
wiring pattern
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP549378A
Other languages
Japanese (ja)
Inventor
Masahiro Oda
Takahiro Honda
Norikuni Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP549378A priority Critical patent/JPS5498575A/en
Publication of JPS5498575A publication Critical patent/JPS5498575A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE: To lower the heat, by saving the power consumption to the circuits not in use, through the use of pattern possible for independent power supply.
CONSTITUTION: The power supply line is fixedly located on the LSI chip master pattern 1. The logic block pattern 2 is selected with the logic block mounting information. The power supply pattern 3 is formed with the logic circuit usage information in the design data and power supply is selectively fed only to the logic block used. The signal wiring pattern 4 wires the parte each logic block with the signal wiring information in the design data. By synthesizing them, the wiring pattern of one LSI can be made. With this constitution, the power supply is made small in size, the cooling is made easy, and the limitation of the degree of integration can be mitigated.
COPYRIGHT: (C)1979,JPO&Japio
JP549378A 1978-01-20 1978-01-20 Wiring pattern forming method of master slice lsi Pending JPS5498575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP549378A JPS5498575A (en) 1978-01-20 1978-01-20 Wiring pattern forming method of master slice lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP549378A JPS5498575A (en) 1978-01-20 1978-01-20 Wiring pattern forming method of master slice lsi

Publications (1)

Publication Number Publication Date
JPS5498575A true JPS5498575A (en) 1979-08-03

Family

ID=11612756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP549378A Pending JPS5498575A (en) 1978-01-20 1978-01-20 Wiring pattern forming method of master slice lsi

Country Status (1)

Country Link
JP (1) JPS5498575A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62113463A (en) * 1985-11-12 1987-05-25 Nec Corp Monolithic integrated circuit
JPH0629502A (en) * 1992-05-12 1994-02-04 Internatl Business Mach Corp <Ibm> Designing method of gate array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62113463A (en) * 1985-11-12 1987-05-25 Nec Corp Monolithic integrated circuit
JPH0629502A (en) * 1992-05-12 1994-02-04 Internatl Business Mach Corp <Ibm> Designing method of gate array

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