JPS5492163A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS5492163A
JPS5492163A JP15948277A JP15948277A JPS5492163A JP S5492163 A JPS5492163 A JP S5492163A JP 15948277 A JP15948277 A JP 15948277A JP 15948277 A JP15948277 A JP 15948277A JP S5492163 A JPS5492163 A JP S5492163A
Authority
JP
Japan
Prior art keywords
input
circuit
point
resistance
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15948277A
Other languages
Japanese (ja)
Inventor
Yuichi Furukawa
Toshihiro Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15948277A priority Critical patent/JPS5492163A/en
Publication of JPS5492163A publication Critical patent/JPS5492163A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE: To delay in input nearly an proportion to variation in resistance value by discharging a capacitor, charged by transistor controlled by the output of a RS type FF circuit, via the transistor or variable resistance.
CONSTITUTION: When the input of set terminal 1A of NAND circuits 11 and 12 constituting the RS type FF circuit becomes "H", transistor Tr1 turns ON via NAND cicuit 13 connected to output terminal 1Q, point P in the circuit becomes "H", and capacitor C1 is charged. With the input "L", charges accumulated in C1 are discharged by Tr2 connected to reference power supply VREF with a constant current, so that the potential at point P will decrease at the time constant determined by C1, resistance R2 and variable resistance Rx. Further, point P is connected to the base of Tr3 connected to reset input terminal 2B of NAND circuit 12 and, in consequence, the potential at point P decreases down to threshold voltage VTH. As a result, output pulse 2Q of circuit 12 becomes "L" and a pulse delayed as compared with the input pulse is outputted in proportion to the variation in resistance Rx.
COPYRIGHT: (C)1979,JPO&Japio
JP15948277A 1977-12-29 1977-12-29 Delay circuit Pending JPS5492163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15948277A JPS5492163A (en) 1977-12-29 1977-12-29 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15948277A JPS5492163A (en) 1977-12-29 1977-12-29 Delay circuit

Publications (1)

Publication Number Publication Date
JPS5492163A true JPS5492163A (en) 1979-07-21

Family

ID=15694726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15948277A Pending JPS5492163A (en) 1977-12-29 1977-12-29 Delay circuit

Country Status (1)

Country Link
JP (1) JPS5492163A (en)

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