JPS5484937A - Protection system for tristate gate - Google Patents

Protection system for tristate gate

Info

Publication number
JPS5484937A
JPS5484937A JP15338177A JP15338177A JPS5484937A JP S5484937 A JPS5484937 A JP S5484937A JP 15338177 A JP15338177 A JP 15338177A JP 15338177 A JP15338177 A JP 15338177A JP S5484937 A JPS5484937 A JP S5484937A
Authority
JP
Japan
Prior art keywords
gate
voltage
fed
power supply
tristate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15338177A
Other languages
Japanese (ja)
Inventor
Tsuguhito Serizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15338177A priority Critical patent/JPS5484937A/en
Publication of JPS5484937A publication Critical patent/JPS5484937A/en
Pending legal-status Critical Current

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  • Direct Current Feeding And Distribution (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To prevent the damage of tristate gate on power supply application, by resetting the latch circuit when the power supply voltage reaches given value, outputting high level signal from the NAND gate, and controlling the control terminal voltage of the tristate gate.
CONSTITUTION: When the power supply is applied, the voltage at the junction of the resistor 6 and the capacitor 7 is gradually started, and this voltage is fed to the reset terminal of the latch circuit 4 via the diode 8. Further, when the power supply voltage reaches a given value, since the reset terminal voltage is at a low level, the circuit 4 is reset and the low level signal is inputted to the NAND gate 5, and the gate 5 outputs high level signal. This signal is fed to the control terminals B1, B2 and B3 of the tristate gates 2-1, 2-2 and 2-3 and the voltage fed to the control terminal after that is controlled with the control signal fed to the gate 5. Thus, the destruction which may be caused on mains application can be prevented.
COPYRIGHT: (C)1979,JPO&Japio
JP15338177A 1977-12-20 1977-12-20 Protection system for tristate gate Pending JPS5484937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15338177A JPS5484937A (en) 1977-12-20 1977-12-20 Protection system for tristate gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15338177A JPS5484937A (en) 1977-12-20 1977-12-20 Protection system for tristate gate

Publications (1)

Publication Number Publication Date
JPS5484937A true JPS5484937A (en) 1979-07-06

Family

ID=15561215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15338177A Pending JPS5484937A (en) 1977-12-20 1977-12-20 Protection system for tristate gate

Country Status (1)

Country Link
JP (1) JPS5484937A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01303826A (en) * 1988-05-31 1989-12-07 Nec Corp Digital signal transmission circuit for multiplexing highway bus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01303826A (en) * 1988-05-31 1989-12-07 Nec Corp Digital signal transmission circuit for multiplexing highway bus
JP2513273B2 (en) * 1988-05-31 1996-07-03 日本電気株式会社 Digital signal transmission circuit in multiplexed highway bus

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