JPH01303826A - Digital signal transmission circuit for multiplexing highway bus - Google Patents

Abstract

PURPOSE:To prevent a dry state gate from being destroyed, and to normally transfer data by starting the sending of a digital signal with an output means when the fact that the potential of a highway bus is in a set potential range is detected with a potential supervising means. CONSTITUTION:Means 120 and 121 to impress a prescribed voltage on a highway bus 100, means to change the potential of a selected channel, means 140 and 141 to supervise the potential of the highway bus 100, and means 160-16n to output digital signals to the highway bus 100 are provided. When the fact that the potential of the highway bus 100 is in the set potential range is detected by the potential supervising means 140 and 141, the output means 160-16n starts the sending of the digital signals. Thus, since the signals are transmitted to the input highway bus 100 after the try state gates 160-16n are completely restored and a high impedance condition is detected, the try state gates can be prevented from colliding, elements can be prevented from being destroyed, and the data can be safely transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal transmission circuit, and more particularly to a collision prevention circuit for inter-channel signals on a highway bus that transmits multiplexed digital signals.

[Conventional technology]

Conventionally, this type of digital signal transmission circuit has had the configuration shown in FIG. Inbound highway bus #1 shown in Figure 3
Figure 2 shows one of the highway buses from #n to #n. The digital signal transmission circuit in Figure 2 is
Tri-state gate 21 on inbound highway bus 200
The configuration is such that data (2) is transmitted through the tri-state gate 210 after completion of transmission of data (2) through n'i.

[Problem to be solved by the invention]

The conventional digital signal transmission circuit shown in FIG.
The configuration is such that data ■ is sent via the . Therefore, in this conventional circuit, data ■ is output from the tri-state gate 210 in a state where the transmission of the tri-state gate 21n is not yet completely completed due to variations in elements, etc. The MS of data ■ whose LSB data is low level and which is the output of the tri-state gate 210
Assuming that the B data is at the no-y level, the output from the tri-state gate 210 to the tri-state gate 21n
There is a problem that a short circuit current flows to the output of the input highway bus 200, and an abnormal current flows on the input highway bus 200, generating an abnormal voltage, and in the worst case, the dry state gate 210.2In is destroyed.

However, if this short-circuit time is short and the signal speed on the input/output path 200, in other words, the signal pulse width is short, damage will not occur due to the electrical strength of the tristate gate element. However, since it was possible to obtain a pulse width sufficient to use the stable waveform after the short-circuit time as data, this did not pose a major problem.

However, as signal speeds increase and signal pulse widths become shorter, tri-state gates require higher power (higher current).
Since a large current flows during this short-circuit time, it is difficult to avoid damage to the element (tri-state gate), and it is not possible to secure a sufficient pulse width to use the stable waveform after the short-circuit time as data. There are problems such as normal data transfer being impossible.

[Failure to solve the problem]

Means provided by the present invention to solve the above problems are as follows:
A circuit for transmitting a digital signal to a multiplexed highway bus, comprising means for applying a predetermined voltage to the freeway path, means for changing the potential of a selected channel, and monitoring the potential of the highway bus. and the means to
means for outputting a digital signal to the highway bus, and when the potential monitoring means detects that the potential of the highway bus is within a set potential range, the output means starts sending out the digital signal. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 1 shows an extracted highway bus from among the high-speed buses #1 to #n shown in FIG. Here, 100 is an incoming highway bus, on which PCM signals and the like are multiplexed and transmitted.

A state in which no signal has arrived at the incoming highway bus 100 (
When the tri-state gates 160 to 16n forming all channels are in a high impedance state, the potential of the input highway bus 100 is 1 of the power supply voltage (+5V).
/2.

The inputs of comparators 140 and 141 for voltage monitoring of this human highway path 100 are connected via a resistor 110, and when no signal has arrived at the input highway bus 100, the tristate gate 160 is in a high impedance state. be. tristate gate 160
When outputting a digital signal (data ■) onto the input highway bus 100 via the input highway bus 100, the tristate gate 16n is transmitting the digital signal (data ■) at a previous assigned timing, and its voltage is at a low level. Then, since current flows through the tristate gate 16n through the resistor 11n, the comparators 140 and 14
Both outputs of 1 become high level, and inverter 150
The output is low level.

The output of the AND gate 151 becomes low level.

Therefore, in this state, the tristate gate 16
When the signal sending pulse is high level at 0, the AND gate 152
, the other input of the AND gate 152 which receives the output of the above-mentioned 151 is at a low level, the output of the AND gate 152 remains at a low level, and the output of the flip 70 knob 153 also remains at a low level. Otherwise, the output of tristate gate 160 also remains in a high impedance state.

Conversely, when the output of the tristate gate 16n is at a high level, the outputs of the comparators 140 and 141 (7) are both at a low level, and the output of the flip-flop 153 also remains at a low level.

The output of tristate gate 160 also remains in a high impedance state.

Then, upon completion of sending data O, the dry state game is activated.
When the output of 16n becomes high impedance, the potential of the input highway bus 100 becomes Z5, which is half of the power supply voltage (+5V).
It will be about V. Then, the output of the comparator 140 and the output of the comparator 141 become low level, and the output of the inverter 150 becomes high level, so the outputs of 151 and 152 also change from low level to 1 level. Therefore, the output Q of the flip-flop 153 is not at a high level and is connected to the input highway bus 1 via the tristate gate 160 and the resistor 110.
Data is output on 00.

In this manner, in this embodiment, it is possible to prevent potential fluctuations brought to the incoming highway bus 100 and destruction of the tristate gates due to abnormal current due to short circuits of the respective tristate gates on the incoming highway bus.

〔Effect of the invention〕

As explained above, in the digital signal transmission circuit of the present invention, when the time to transmit a signal on the incoming highway bus arrives, the tristate gate that was connected and was transmitting the signal before the arrival of the transmission time arrives. A signal is sent to the human highway bus only after it has completely recovered and detected a high impedance state, which prevents collisions between tri-state gates, which in turn prevents element destruction and allows stable data transmission. .

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional digital signal transmission circuit, and Fig. 3 is the basics of a general digital signal transmission system in which a digital signal transmission circuit is used. FIG. 3 is a diagram showing the configuration. 100.200...Highway bus, 110~ll
n. 120.121...Resistor connected to input highway bus 100, 140, 141...Comparator, 130
゜131.132...Comparator (140,141
) resistance constituting the bias, 150...inverter gate, 151.152...and gate, 153.
...Flip-flop, 160~16n, 210~2
1rl...tristate gate. Agent Patent Attorney Shinsuke Honjo Figure 3

Claims (1)

[Claims] A circuit for transmitting a digital signal to a multiplexed highway bus, comprising means for applying a predetermined voltage to the highway bus, means for changing the potential of a selected channel, and means for monitoring the potential of the highway bus. ,
means for outputting a digital signal to the highway bus, and when the potential monitoring means detects that the potential of the highway bus is within a set potential range, the output means starts sending out the digital signal. A digital signal transmission circuit for a multiplexed highway bus, characterized in that: