JPS5481731A - Clock and refresh control system for dynamic type memory - Google Patents

Clock and refresh control system for dynamic type memory

Info

Publication number
JPS5481731A
JPS5481731A JP14973577A JP14973577A JPS5481731A JP S5481731 A JPS5481731 A JP S5481731A JP 14973577 A JP14973577 A JP 14973577A JP 14973577 A JP14973577 A JP 14973577A JP S5481731 A JPS5481731 A JP S5481731A
Authority
JP
Japan
Prior art keywords
clock
refresh request
cpu
memory
different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14973577A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6155196B2 (enrdf_load_stackoverflow
Inventor
Haruhiko Tsunoda
Kiyokatsu Iijima
Takashi Kawakami
Katsuhiko Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP14973577A priority Critical patent/JPS5481731A/ja
Publication of JPS5481731A publication Critical patent/JPS5481731A/ja
Publication of JPS6155196B2 publication Critical patent/JPS6155196B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
JP14973577A 1977-12-13 1977-12-13 Clock and refresh control system for dynamic type memory Granted JPS5481731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14973577A JPS5481731A (en) 1977-12-13 1977-12-13 Clock and refresh control system for dynamic type memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14973577A JPS5481731A (en) 1977-12-13 1977-12-13 Clock and refresh control system for dynamic type memory

Publications (2)

Publication Number Publication Date
JPS5481731A true JPS5481731A (en) 1979-06-29
JPS6155196B2 JPS6155196B2 (enrdf_load_stackoverflow) 1986-11-26

Family

ID=15481657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14973577A Granted JPS5481731A (en) 1977-12-13 1977-12-13 Clock and refresh control system for dynamic type memory

Country Status (1)

Country Link
JP (1) JPS5481731A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230258A (ja) * 1984-04-27 1985-11-15 Panafacom Ltd マルチプロセツサのメモリ制御方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230258A (ja) * 1984-04-27 1985-11-15 Panafacom Ltd マルチプロセツサのメモリ制御方式

Also Published As

Publication number Publication date
JPS6155196B2 (enrdf_load_stackoverflow) 1986-11-26

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