JPS5469325A - Time base correction equipment - Google Patents

Time base correction equipment

Info

Publication number
JPS5469325A
JPS5469325A JP13688477A JP13688477A JPS5469325A JP S5469325 A JPS5469325 A JP S5469325A JP 13688477 A JP13688477 A JP 13688477A JP 13688477 A JP13688477 A JP 13688477A JP S5469325 A JPS5469325 A JP S5469325A
Authority
JP
Japan
Prior art keywords
output
time base
oscillator
supplied
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13688477A
Other languages
Japanese (ja)
Inventor
Kaneyoshi Sugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13688477A priority Critical patent/JPS5469325A/en
Publication of JPS5469325A publication Critical patent/JPS5469325A/en
Pending legal-status Critical Current

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  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Abstract

PURPOSE: To obtain a time base correction equipment which can satisfy the NTSC standard even if it is combined with general VTR by controlling it by means of the clock which enters time delay and setting the analog varialbe delay line which delays the input having time base variation.
CONSTITUTION: Synchronizing separator 2 which can apply synchronizing separation to the input signal with time base variation to be given to terminal 11, first phase comparator 3 which can generate subcarrier with the special relation to a synchronizing signal and voltage control oscillator 5 which is controlled by the output of comparator 3 are attached and the output of oscillator 5 is supplied to VTR through teminal 12. The output of oscillator 5 is supplied to second phase comparator 6 and is compared with the standard subcarrier of terminal 15. Moreover, the output of separator 2 is supplied to third phase comparator 7 and is phase- compared with the standard synchronizing signal of terminal 16; both outputs of comparators 6 and 7 are added by adder 8 and error voltage is induced. Then, variable frequency oscillator 9 which generates clock signals is controlled and time delay of analog variable delay line 1 is also controlled, so that errors can be corrected.
COPYRIGHT: (C)1979,JPO&Japio
JP13688477A 1977-11-14 1977-11-14 Time base correction equipment Pending JPS5469325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13688477A JPS5469325A (en) 1977-11-14 1977-11-14 Time base correction equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13688477A JPS5469325A (en) 1977-11-14 1977-11-14 Time base correction equipment

Publications (1)

Publication Number Publication Date
JPS5469325A true JPS5469325A (en) 1979-06-04

Family

ID=15185789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13688477A Pending JPS5469325A (en) 1977-11-14 1977-11-14 Time base correction equipment

Country Status (1)

Country Link
JP (1) JPS5469325A (en)

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