JPS5467750A - Pll lock detector circuit - Google Patents

Pll lock detector circuit

Info

Publication number
JPS5467750A
JPS5467750A JP13499577A JP13499577A JPS5467750A JP S5467750 A JPS5467750 A JP S5467750A JP 13499577 A JP13499577 A JP 13499577A JP 13499577 A JP13499577 A JP 13499577A JP S5467750 A JPS5467750 A JP S5467750A
Authority
JP
Japan
Prior art keywords
output
signal
sent
detector circuit
lock detector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13499577A
Other languages
Japanese (ja)
Inventor
Tadashi Kojima
Kouichirou Satou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13499577A priority Critical patent/JPS5467750A/en
Publication of JPS5467750A publication Critical patent/JPS5467750A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Abstract

PURPOSE:To perform a high-certainty PLL (phase synchronizing loop) lock detection. CONSTITUTION:Signal fr' from reference frequency divider 12 is supplied to D-type flip-flop F1, and the Q1 output delayed by this F1 is used as reference signal fr sent to phase comparator 15a and is supplied to another F2 to obtain the Q2 output delayed further. The Q2 output is sent to NAND gate NG2 as fr'' together with the signal obtained by causing signal fr' from frequency divider 12 to pass through inverter I1. Measnwhile, output MG from NG2 is sent to AND gate A1 together with phase error output P-O obtained from NG1 of comparator 15a. That is, the P-O output is masked with MG signals, and the L-DG output is generated from A1 only when the P-O output is over the width of MG signals. Then, switch SW is closed by this output to charge a capactor.
JP13499577A 1977-11-10 1977-11-10 Pll lock detector circuit Pending JPS5467750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13499577A JPS5467750A (en) 1977-11-10 1977-11-10 Pll lock detector circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13499577A JPS5467750A (en) 1977-11-10 1977-11-10 Pll lock detector circuit

Publications (1)

Publication Number Publication Date
JPS5467750A true JPS5467750A (en) 1979-05-31

Family

ID=15141469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13499577A Pending JPS5467750A (en) 1977-11-10 1977-11-10 Pll lock detector circuit

Country Status (1)

Country Link
JP (1) JPS5467750A (en)

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