JPS5462798A - Centralized alarm and monitor device - Google Patents

Centralized alarm and monitor device

Info

Publication number
JPS5462798A
JPS5462798A JP12943577A JP12943577A JPS5462798A JP S5462798 A JPS5462798 A JP S5462798A JP 12943577 A JP12943577 A JP 12943577A JP 12943577 A JP12943577 A JP 12943577A JP S5462798 A JPS5462798 A JP S5462798A
Authority
JP
Japan
Prior art keywords
input
trouble
cpu1
cpu2
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12943577A
Other languages
Japanese (ja)
Inventor
Akihiro Yamada
Norio Miyawaki
Tetsuo Doi
Yasushi Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP12943577A priority Critical patent/JPS5462798A/en
Publication of JPS5462798A publication Critical patent/JPS5462798A/en
Pending legal-status Critical Current

Links

Landscapes

  • Audible And Visible Signals (AREA)
  • Alarm Systems (AREA)
  • Selective Calling Equipment (AREA)

Abstract

PURPOSE: To display an alarm even for a trouble occurring and disappearing in a short period of time by providing read-only control device in the case of central control of a pair of trouble detector group and display device by sequential scanning method.
CONSTITUTION: A read-only control device CPU2 generates interrupt signals to a central control device CPU1 at proper intervals of time, and scans all input ports I of trouble detectors D1 to Dn at high speed within the interruption period, thereby recording presence or absence of input (trouble detection signals) to the corresponding addresses of memory RAM. The CPU1 sequentially reads the contents in each address of RAM during the interrupt signal period given by the CPU2, and sends control signals to corresponding display lamps L1 to Ln. The CPU2 counts the interrupt signals in a label counter of proper counting range, and when inputs are applied to input port I, the counting output, together with the input signal, is written into the corresponding address of RAM. Comparing with the counting output read out at each scanning, when the outputs are in coincidence, the address contents is made to 0, as far as there is no input in the corresponding input point. Therefore, the input is maintained during the period of several scannings, so that the input may not escape the reading of CPU1.
COPYRIGHT: (C)1979,JPO&Japio
JP12943577A 1977-10-27 1977-10-27 Centralized alarm and monitor device Pending JPS5462798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12943577A JPS5462798A (en) 1977-10-27 1977-10-27 Centralized alarm and monitor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12943577A JPS5462798A (en) 1977-10-27 1977-10-27 Centralized alarm and monitor device

Publications (1)

Publication Number Publication Date
JPS5462798A true JPS5462798A (en) 1979-05-21

Family

ID=15009399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12943577A Pending JPS5462798A (en) 1977-10-27 1977-10-27 Centralized alarm and monitor device

Country Status (1)

Country Link
JP (1) JPS5462798A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58116897A (en) * 1981-12-29 1983-07-12 Matsushita Electric Works Ltd Time-division multiplex transmission system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58116897A (en) * 1981-12-29 1983-07-12 Matsushita Electric Works Ltd Time-division multiplex transmission system
JPS6340079B2 (en) * 1981-12-29 1988-08-09 Matsushita Electric Works Ltd

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