JPS5461449A - D type flip flop circuit - Google Patents

D type flip flop circuit

Info

Publication number
JPS5461449A
JPS5461449A JP12751077A JP12751077A JPS5461449A JP S5461449 A JPS5461449 A JP S5461449A JP 12751077 A JP12751077 A JP 12751077A JP 12751077 A JP12751077 A JP 12751077A JP S5461449 A JPS5461449 A JP S5461449A
Authority
JP
Japan
Prior art keywords
circuit
misfet
latch
latch circuits
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12751077A
Other languages
Japanese (ja)
Inventor
Akira Takanashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12751077A priority Critical patent/JPS5461449A/en
Publication of JPS5461449A publication Critical patent/JPS5461449A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To establish the D type FF circuit adding the refresh functions to the signal at opposite potential as the substrate potential of MISFET, by using the latch circuit constituted with the load and the drive MISFET in parallel connection. CONSTITUTION:The circuit is provided with the first and second latch circuits G1, G2,G3 and G4 constituted with the driving MISFET in parallel connection with the load and the first and second delivery gate MISFET Q1 and Q2 placed at another input of one logic circuit of those latch circuits. Further, the first clock pulse phi1 and second clock pulse phi2 for D type FF operation are fed to the delivery gate MISFET and the latch circuit. Then, input signal is fed via the first gate Q1, the output B of one logic circuit of the first latch circuits G1 and G2 is fed to the second latch circuits G3 and G4 via the second delivery gate Q2, and the output of the latch circuit is taken as the output Q.
JP12751077A 1977-10-26 1977-10-26 D type flip flop circuit Pending JPS5461449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12751077A JPS5461449A (en) 1977-10-26 1977-10-26 D type flip flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12751077A JPS5461449A (en) 1977-10-26 1977-10-26 D type flip flop circuit

Publications (1)

Publication Number Publication Date
JPS5461449A true JPS5461449A (en) 1979-05-17

Family

ID=14961773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12751077A Pending JPS5461449A (en) 1977-10-26 1977-10-26 D type flip flop circuit

Country Status (1)

Country Link
JP (1) JPS5461449A (en)

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