JPS5447536A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5447536A
JPS5447536A JP11336877A JP11336877A JPS5447536A JP S5447536 A JPS5447536 A JP S5447536A JP 11336877 A JP11336877 A JP 11336877A JP 11336877 A JP11336877 A JP 11336877A JP S5447536 A JPS5447536 A JP S5447536A
Authority
JP
Japan
Prior art keywords
terminal
signal
irq
cpu1
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11336877A
Other languages
Japanese (ja)
Inventor
Shiro Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11336877A priority Critical patent/JPS5447536A/en
Publication of JPS5447536A publication Critical patent/JPS5447536A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce to number of the terminal in the integrated circuit and thus to realize a miniature size of the chip, by using one unit of the terminal in the peripheral integrated circuit for the transmission of the interruption request and the signal which is generated only while the CPU is stopped.
CONSTITUTION: CPU1 is connected to direct memory access controller 2, and controller 2 is connected to other peripheral chips 5W7 via inverter 3a and 3b plus NAND circuit 4a. Then the terminal of interruption output -IRQ is chips 5W7 is connected to the terminal of interruption input -IRQ of CPU1, and the IRQ output terminal of controller 2 is used for transmission of -DEND signal of CPU1. When function switch signal BA of CPU1 is "1", the signal of terminal -IRQ/-DEND of controller 2 is transmitted to -DEND line and is transmitted to -IRQ signal line when signal BA is "0" respectively
COPYRIGHT: (C)1979,JPO&Japio
JP11336877A 1977-09-22 1977-09-22 Information processor Pending JPS5447536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11336877A JPS5447536A (en) 1977-09-22 1977-09-22 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11336877A JPS5447536A (en) 1977-09-22 1977-09-22 Information processor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP3237084A Division JPS6024665A (en) 1984-02-24 1984-02-24 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5447536A true JPS5447536A (en) 1979-04-14

Family

ID=14610500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11336877A Pending JPS5447536A (en) 1977-09-22 1977-09-22 Information processor

Country Status (1)

Country Link
JP (1) JPS5447536A (en)

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