JPS5444844A - Control system for bus occupancy - Google Patents

Control system for bus occupancy

Info

Publication number
JPS5444844A
JPS5444844A JP10769977A JP10769977A JPS5444844A JP S5444844 A JPS5444844 A JP S5444844A JP 10769977 A JP10769977 A JP 10769977A JP 10769977 A JP10769977 A JP 10769977A JP S5444844 A JPS5444844 A JP S5444844A
Authority
JP
Japan
Prior art keywords
bus
occupancy
rank
occupancy request
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10769977A
Other languages
Japanese (ja)
Other versions
JPS5756734B2 (en
Inventor
Masamitsu Miyazaki
Yoshihito Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP10769977A priority Critical patent/JPS5444844A/en
Publication of JPS5444844A publication Critical patent/JPS5444844A/en
Publication of JPS5756734B2 publication Critical patent/JPS5756734B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To improve the availability of each device and the processing function of the entire system by making the operation inhibit control on a constant cycle against the processing of a higher-rank bus occupancy request in case of the occurrence of a lower-rank bus occupancy request.
CONSTITUTION: The circuit is provided with latch circuits L1 to Ln stored with bus-occupancy request signal antis RQ0 to RQn, FFs 1F1 to 1Fn for priority control of bus occupancy J-KFFs 2F1 to 2Fn which output bus-occupancy permitting signal antis S0 to Sn, and gate circuits 1G1 to 1Gn which inhibit the bus-occupancy permission of the lower-rank device. Then, even if a new higher-rank bus-occupancy request is made during the latency time of the lower bus-occupancy request process, the process is inhibited for a "L"-level period through the inversion with duty 50% of J-KFFs 3F1 to 3Fn-1. Therefore, losing bus-occupancy service to a device assigned to a lower rank is eliminated, and the higher-rank priority function can be attained without trouble.
COPYRIGHT: (C)1979,JPO&Japio
JP10769977A 1977-09-09 1977-09-09 Control system for bus occupancy Granted JPS5444844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10769977A JPS5444844A (en) 1977-09-09 1977-09-09 Control system for bus occupancy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10769977A JPS5444844A (en) 1977-09-09 1977-09-09 Control system for bus occupancy

Publications (2)

Publication Number Publication Date
JPS5444844A true JPS5444844A (en) 1979-04-09
JPS5756734B2 JPS5756734B2 (en) 1982-12-01

Family

ID=14465703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10769977A Granted JPS5444844A (en) 1977-09-09 1977-09-09 Control system for bus occupancy

Country Status (1)

Country Link
JP (1) JPS5444844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH096730A (en) * 1995-06-14 1997-01-10 Kofu Nippon Denki Kk Multiple processor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4898739A (en) * 1972-03-27 1973-12-14
JPS505009A (en) * 1973-03-29 1975-01-20
JPS52132748A (en) * 1976-04-30 1977-11-07 Hitachi Ltd Information i/o control system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4898739A (en) * 1972-03-27 1973-12-14
JPS505009A (en) * 1973-03-29 1975-01-20
JPS52132748A (en) * 1976-04-30 1977-11-07 Hitachi Ltd Information i/o control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH096730A (en) * 1995-06-14 1997-01-10 Kofu Nippon Denki Kk Multiple processor

Also Published As

Publication number Publication date
JPS5756734B2 (en) 1982-12-01

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