JPH096730A - Multiple processor - Google Patents

Abstract

PURPOSE: To reduce overhead due to the parallel operations of plural operating systems(OS) on one system as much as possible. CONSTITUTION: A processor and a main storage device are provided with means for holding their own device identification numbers and means for holding the group identification numbers of OS to which those devices belong, and the controller of a bus is provided with a group information storage buffer 102 for holding the information of relations between the group identification numbers and the device identification numbers, means 103-106 for deciding the group identification number of the OS to enable the usage of the bus for each bus cycle, and bus arbiter circuit for deciding the device to use the bus from bus utilizing requests from the processor and the main storage device and the relation information read by the decided group identification number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system for executing a plurality of operating systems (OS) in parallel on a bus-connected multiprocessor system.

[0002]

2. Description of the Related Art Generally, when executing application software on two different OSs in parallel on one system, or when developing a new OS while an old OS is running, a virtual computer is used. It is conventionally known to use a system. In this case, a plurality of virtual processing units (VM) are generated on the actual processing unit by using the control program and the hardware function for realizing the virtual computer system, and each virtual processing unit (VM) is generated on the VM.
S can be executed.

[0003]

In the above-mentioned conventional multiprocessor, it is essential to develop a VM control program for controlling the VM. Further, in order to guarantee independence between VMs, a privileged instruction that changes the state of the processing device that issued the program on the VM is not directly executed by the actual processing device, and the VM control program changes the state of the VM. I am simulating. Therefore, there is a problem in that the overhead related to the privileged instruction is large and the performance is significantly reduced as compared with the case where the privileged instruction is directly executed by the processing device. In order to reduce this performance deterioration, usually, the speed-up function for VM control is realized by using hardware and firmware.

By the way, in a multiprocessor system, by allocating an OS to each processor group, it is possible to operate a plurality of OSs in parallel in one system, and therefore a virtual storage computer system is unnecessary. However, since the system bus for interfacing each arithmetic processing unit, the input / output unit, and the main storage unit is shared, conventionally, in order to guarantee independence between OSs,
A mechanism for recognizing which OS the transaction on the system bus belongs to, for example, an identification number for each device is given to the transaction on the system bus, and each device subordinates the OS to which it belongs. It is necessary to determine whether or not the transaction is a transaction and activate the function of the own device in the transaction, which causes a problem that the amount of hardware to be invested is large.

[0005]

SUMMARY OF THE INVENTION An apparatus according to the present invention comprises a plurality of operating systems arranged in parallel on an information processing apparatus in which a plurality of processing units, one or more main storage units, and a bus control unit are connected by a bus. In the multi-processing device for executing the above, the processing device and the main storage device are provided with means for holding a device identification number of its own device and means for holding a group identification number of an operating system to which the device belongs, and The bus control device holds a relationship information between the group identification number and the device identification number, a means for determining a group identification number of an operating system that can use the bus for each bus cycle, the processing device and the main unit. Bus usage device from a bus usage request from a storage device and the relationship information read by the determined group identification number Multiprocessing apparatus characterized in that a means for determining.

[0006]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing an example of a multiprocessor system configuration to which the present invention is applied. In FIG. 3, the arithmetic processing units (CPU) 1, 2, 3, 4, main storage units (MMU) 5, 6, input / output units (IOP) 7, 8 and system bus control unit (SBC) 9 are the system bus 1
00 for connection. System bus 100 is SB
The signal line is controlled by C9 and bidirectionally transfers information between devices 1 to 9 connected by the system bus 100. The signal lines 301 to 308 are from the respective devices 1 to 8 connected to the system bus 100 except the SBC 9,
This is for making a bus use request to the SBC 9.

The operation of this system will be described with reference to the timing chart shown in FIG. 4, focusing on the function of the system bus. 4 cycles per system bus 100
Composed of a clock. First, T0 is the system bus 10
This is the timing of issuing a system bus use request from each of the devices 1 to 8 connected to 0 to the SBC 9. At this time, each of the devices 1 to 8 issues a request to the SBC 9 using the connection lines 301 to 308 of FIG. Next, at T1, S
The BC9 performs arbitration based on the bus use request received from the devices 1 to 8 at T0, and assigns the device number that permits the use of the bus in the cycle to the entire device 1 via the system bus 100.
Broadcast to ~ 8. At T2 and T3, a device permitted to use the bus issues information to the system bus 100. T4 ~
T7 is the repetition of the above processing performed in T0 to T3.

Next, as an example of the timing chart of FIG. 4, FIG. 5 shows a case where a main memory read request is issued from the CPU 1 to the MMU 5. When an access request is generated in cycle 1, the CPU 1 issues a system bus use request to the SBC 9 using the connection line 301 at T0. SBC9 is CP via system bus 100 at T1
Give U1 permission to use the system bus. CPU1 is T
At 2, T3, a main memory read request and a request address are issued to the MMU5. In cycle 2, since the read data for the main memory read request requested in cycle 1 is returned, the MMU 5 sends the connection line 301 to the SBC 9 at T4.
Is used to issue a system bus use request. The SBC 9 gives the system bus use permission to the MMU 5 via the system bus 100 at T5. MMU5 is CPU at T2, T3
The main storage read data is issued to 1.

Next, a case where each of the devices 1 to 8 belonging to the present multiprocessor system is divided and operates under the control of a plurality of OSs will be described. FIG. 6 is a diagram showing grouping of devices when each device is divided and operates under the control of two OSs in the system configuration shown in FIG.
CPU1, CPU2, MMU5 and IO included in 01
P7 (group A) and CPU included in area 602
3, CPU4, MMU6 and IOP8 (Group B)
Operate under different OSs.

The operation of the system bus in this state will be described with reference to the timing chart shown in FIG. The right to use the system bus 100 is allocated by the SBC 9 to two device groups under the OS every bus cycle. In this case, in the timing chart, the odd cycle is allocated to the device of group A and the even cycle is allocated to the device of group B.

In cycle 1, a main memory read request is issued by CPU1 and CPU3, and CPU1 and CPU3 execute S at T0.
A system bus use request is issued to the BC 9 using the connection lines 301 and 303, respectively. The SBC 9 determines that the group A has the bus use right in the cycle 1, and broadcasts that the bus use permission is given to the CPU 1 of the group A to all the devices 1 to 8 via the system bus 100 at T1. The CPU 1 issues a main memory read request and a request address to the MMU 5 at T2 and T3. The other devices belonging to the group A receive the request issued from the CPU 1 and operate. The devices belonging to group B do nothing.

In cycle 2, the main memory read request is issued from the CPU 3, the main memory data reply request is issued from the MMU 5, and the CPU 3 and the MMU 5 use the system bus to the SBC 9 at T4 by using the connection lines 303 and 305, respectively. Make a request. The SBC 9 determines that the group B has the right to use the bus in the cycle 2, and at T5, the CP of the group B is sent to all the devices 1 to 8 via the system bus 100.
Broadcast that U3 has been granted bus permission. CPU3
Issues a main memory read request and request address to the MMU 6 at T6 and T7. The other devices belonging to the group B receive the request issued from the CPU 3 and operate. Devices belonging to group A do nothing.

In cycle 3, main memory data reply requests are issued from MMU5 and MMU6, and MMU5 and MMU6
Is connected to SBC9 at T8 by connecting lines 305 and 3 respectively.
A system bus use request is issued using 06. SBC
In cycle 9, it is determined that the group A has the bus use right in the cycle 3, and broadcasts that the bus use permission is given to the MMU 5 of the group A to all the devices 1 to 8 through the system bus 100 at T9. The MMU 5 issues main memory read data to the CPU 1 at T10 and T11. The other devices belonging to the group A perform the operation upon receiving the request issued from the MMU 5. The devices belonging to group B do nothing.

In cycle 4, the main memory data reply request is generated from the MMU 6, and the MMU 6 issues a system bus use request to the SBC 9 using the connection line 306 at T12. The SBC 9 determines that the group A has the bus use right in the cycle 3, and broadcasts that the bus use permission is given to the MMU 6 of the group B to all the devices 1 to 8 through the system bus 100 at T13. MMU6 is T14, T
At 15, the main memory read data is issued to the CPU 3. The other devices belonging to the group B receive the request issued from the MMU 6 and operate. The devices belonging to group B do nothing.

Next, the operation described above will be described with reference to the detailed diagram of the SBC 9 shown in FIG. 1 and the detailed diagram of the system bus interface section of each of the devices 1 to 8 shown in FIG.

Group information storage buffer 1 in FIG.
Reference numeral 02 denotes a buffer composed of 8 bits × 2 words, which holds information indicating a relationship to which OS group each of the devices 1 to 8 set at system startup in advance belongs. The bus available group designation register 103 indicates a group number that has the usage right in the bus cycle, and the counter 104 increments the count for each bus cycle. The register 305 is a register that stores the number of OS groups. "0" is set when the OS has one configuration, and "1" is set when the OS has two configurations. The comparator 106 includes registers 103 and 105.
And the values in the register 103 are reset to "0".

The group number indicated by the register 103 corresponds to the group information storage buffer 1 through the connection line 110.
02 read address. The device information having the bus use right read from the group information storage buffer 102 is input to the AND circuit group 107. In the AND circuit group 107, the logical product of the bus acquisition request signals 301 to 308 issued from the respective devices 1 to 8 and the device information having the bus use right is calculated for each device, and the connection line 111 informs the bus arbitration circuit 101. Is entered. System bus arbitration circuit 10
1 receives the bus use request signal 111 as an input,
8) Arbitration is performed to determine the bus usable device in each bus cycle. The determined bus available group number and device number are broadcast to all devices 1 to 8 via the system bus 100.

Next, the system bus interface section of each of the devices 1 to 8 connected to the system bus 100 shown in FIG. 2 will be described by taking the CPU 1 as an example. The bus interface circuit 201 is a circuit that is located between the processing device 202 and the system bus 100 and performs interface control. The register 203 is a register that holds the OS group number to which the CPU 1 belongs, and its value is set when the system is started. The register 204 is a register that holds the device number of the CPU 1, and its value is set when the system is activated.

The comparator 205 is a bus available group number sent from the system bus controller 9 via the system bus 101 every bus cycle and the register 203.
Are compared, and the result is compared to the bus interface circuit 20.
Report to 1. The bus interface circuit 201 receives the result and determines whether or not the bus cycle is a cycle that can be used by the group to which the bus interface circuit 201 belongs. Further, the comparator 206 uses the bus available device number and the register 2 sent from the system bus control device 9 every bus cycle.
04 is compared and the result is reported to the bus interface circuit 201. The bus interface circuit 201 receives the result and determines whether or not the bus cycle is a cycle in which its own bus access request can be issued.
The same applies to the other devices 2 to 8.

[0020]

As described above, according to the present invention,
It is possible to execute a plurality of OSs in parallel on a multiprocessor system without requiring the function of the virtual computer system. Furthermore, by adding a minimum hardware function to the control circuit of the system bus, independence between OSs is guaranteed, and the overhead due to a plurality of OSs operating in parallel on one system can be minimized. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a system controller according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a system bus interface unit in an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a multiprocessor system to which the present invention is applied.

FIG. 4 is a general timing chart under 1OS in the present invention.

5 is a timing chart showing a specific example of the timing chart shown in FIG.

FIG. 6 is a diagram showing grouping of a multiprocessor system to which the present invention is applied.

FIG. 7 is a timing chart showing an operation example under 2OS in the present invention.

[Explanation of symbols]

 1,2,3,4 Arithmetic processing unit (CPU) 5,6 Main memory unit (MMU) 7,8 Input / output unit (IOP) 9 System bus control unit (SBC) 100 System bus 101 System bus arbitration circuit 102 Group information Storage buffer 103 Bus usable group designation register 104 Counter 105, 203, 204 Register 106, 205, 206 Comparator 107 AND circuit group 201 Bus interface circuit 202 Processing device 110, 111, 301-308 Connection line

Claims (1)

[Claims] 1. A multi-processing device that executes a plurality of operating systems in parallel on an information processing device in which a plurality of processing devices, one or more main storage devices, and a bus control device are bus-connected, The device and the main storage device are provided with means for holding the device identification number of the device itself and means for holding the group identification number of the operating system to which the device belongs, and the bus control device is provided with the group identification number. Means for holding the relationship information between the device identification number and the device identification number, a means for determining the group identification number of the operating system that can use the bus for each bus cycle, a bus use request from the processing device and the main storage device, and the determination Means for determining a bus using device from the related information read by the group identification number Multiprocessing apparatus according to symptoms.