JPS5444839A - Character pattern generator - Google Patents

Character pattern generator

Info

Publication number
JPS5444839A
JPS5444839A JP11138777A JP11138777A JPS5444839A JP S5444839 A JPS5444839 A JP S5444839A JP 11138777 A JP11138777 A JP 11138777A JP 11138777 A JP11138777 A JP 11138777A JP S5444839 A JPS5444839 A JP S5444839A
Authority
JP
Japan
Prior art keywords
read
circuit
signal
character pattern
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11138777A
Other languages
Japanese (ja)
Inventor
Hideo Sakamoto
Sakae Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11138777A priority Critical patent/JPS5444839A/en
Publication of JPS5444839A publication Critical patent/JPS5444839A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To read a character pattern vertically and horizontally at a high speed by a character pattern generator, which is able to read patterns vertically and horizontally, by improving the read speed by eliminating the conversion of data by a buffer memory.
CONSTITUTION: This device is equipped with character pattern memory circuit 11 which decomposes several character patterns into dot matrixes of a P number of bits making it possible to read them in either vertical or horizontal direction under the control of computer 12 and is stored with those decomposed character patterns on a P2-bit unit, and address converter circuit 21 which generates a conversion address by converting the address signal from the vertical direction to the horizontal direction or in reverse. Then, selector circuit 22 is provided which selects the conversion signal from circuit 21 and by a read-direction assignment signal and sends the selected signal to circuit 11, and further, multiplexer 23 is also provided which receives P2-bit unit signals from circuit 11 at one input terminal in the sequence of vertical direction and at the other input terminal in the sequence of horizontal reading to generate character patterns by selecting the read-out direction by a read- direction assignment signal.
COPYRIGHT: (C)1979,JPO&Japio
JP11138777A 1977-09-16 1977-09-16 Character pattern generator Pending JPS5444839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11138777A JPS5444839A (en) 1977-09-16 1977-09-16 Character pattern generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11138777A JPS5444839A (en) 1977-09-16 1977-09-16 Character pattern generator

Publications (1)

Publication Number Publication Date
JPS5444839A true JPS5444839A (en) 1979-04-09

Family

ID=14559882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11138777A Pending JPS5444839A (en) 1977-09-16 1977-09-16 Character pattern generator

Country Status (1)

Country Link
JP (1) JPS5444839A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031178A (en) * 1983-07-29 1985-02-16 日本電気株式会社 Display controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031178A (en) * 1983-07-29 1985-02-16 日本電気株式会社 Display controller

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