JPS5444448A - Interruption acknowledge system - Google Patents

Interruption acknowledge system

Info

Publication number
JPS5444448A
JPS5444448A JP11084377A JP11084377A JPS5444448A JP S5444448 A JPS5444448 A JP S5444448A JP 11084377 A JP11084377 A JP 11084377A JP 11084377 A JP11084377 A JP 11084377A JP S5444448 A JPS5444448 A JP S5444448A
Authority
JP
Japan
Prior art keywords
cpu
level
gate
interrupt
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11084377A
Other languages
Japanese (ja)
Inventor
Ryuji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP11084377A priority Critical patent/JPS5444448A/en
Publication of JPS5444448A publication Critical patent/JPS5444448A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To quickly specify the I/O performing interrupt request, by providing the acknowledge FF to a plural number of I/O's connected to CPR, and by generating the acknowledge FF lead signal from CPU.
CONSTITUTION: When interrupt request is made from IK/OIO-1, IO-2..., the interrupt signal INT is made to CPU, and simultaneously the acknowldege FFACKFF is set, and the input terminal of the gate RG for lead connected to the Q terminal is at H level. Further, one input terminal of the gate TG for test is at H level. When CPU develops the signal ACK, the bits in the data bus DTA connected to the gate RG of which input is at H level are at H level and specify the I/O requested for interrupt with th register of CPU read in. Next, when CPU generates the signal TST, it is fetched to CPU through the bus DTA from the gate TG of which input is at H level, and the interrupt factor of I/O is detected.
COPYRIGHT: (C)1979,JPO&Japio
JP11084377A 1977-09-14 1977-09-14 Interruption acknowledge system Pending JPS5444448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11084377A JPS5444448A (en) 1977-09-14 1977-09-14 Interruption acknowledge system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11084377A JPS5444448A (en) 1977-09-14 1977-09-14 Interruption acknowledge system

Publications (1)

Publication Number Publication Date
JPS5444448A true JPS5444448A (en) 1979-04-07

Family

ID=14546062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11084377A Pending JPS5444448A (en) 1977-09-14 1977-09-14 Interruption acknowledge system

Country Status (1)

Country Link
JP (1) JPS5444448A (en)

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