JPS5438468U - - Google Patents

Info

Publication number
JPS5438468U
JPS5438468U JP1977111739U JP11173977U JPS5438468U JP S5438468 U JPS5438468 U JP S5438468U JP 1977111739 U JP1977111739 U JP 1977111739U JP 11173977 U JP11173977 U JP 11173977U JP S5438468 U JPS5438468 U JP S5438468U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1977111739U
Other versions
JPS5636140Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1977111739U priority Critical patent/JPS5636140Y2/ja
Priority to GB7830237A priority patent/GB2002967B/en
Publication of JPS5438468U publication Critical patent/JPS5438468U/ja
Application granted granted Critical
Publication of JPS5636140Y2 publication Critical patent/JPS5636140Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP1977111739U 1977-08-19 1977-08-19 Expired JPS5636140Y2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1977111739U JPS5636140Y2 (ja) 1977-08-19 1977-08-19
GB7830237A GB2002967B (en) 1977-08-19 1978-07-18 Integrated circuit assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977111739U JPS5636140Y2 (ja) 1977-08-19 1977-08-19

Publications (2)

Publication Number Publication Date
JPS5438468U true JPS5438468U (ja) 1979-03-13
JPS5636140Y2 JPS5636140Y2 (ja) 1981-08-25

Family

ID=14568949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977111739U Expired JPS5636140Y2 (ja) 1977-08-19 1977-08-19

Country Status (2)

Country Link
JP (1) JPS5636140Y2 (ja)
GB (1) GB2002967B (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141338A (en) * 1981-02-26 1982-09-01 Purakoo:Kk Method and apparatus to wind up synthetic resin film
JPS58169950A (ja) * 1982-03-31 1983-10-06 Toshiba Corp マルチチップモジュール

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2204184A (en) * 1987-04-29 1988-11-02 Stanley Bracey Mounting electronic components on substrates

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5019360A (ja) * 1973-06-20 1975-02-28

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5019360A (ja) * 1973-06-20 1975-02-28

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141338A (en) * 1981-02-26 1982-09-01 Purakoo:Kk Method and apparatus to wind up synthetic resin film
JPS58169950A (ja) * 1982-03-31 1983-10-06 Toshiba Corp マルチチップモジュール

Also Published As

Publication number Publication date
JPS5636140Y2 (ja) 1981-08-25
GB2002967A (en) 1979-02-28
GB2002967B (en) 1982-01-06

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