JPS5416138A - Nonvolatile memory - Google Patents

Nonvolatile memory

Info

Publication number
JPS5416138A
JPS5416138A JP8043177A JP8043177A JPS5416138A JP S5416138 A JPS5416138 A JP S5416138A JP 8043177 A JP8043177 A JP 8043177A JP 8043177 A JP8043177 A JP 8043177A JP S5416138 A JPS5416138 A JP S5416138A
Authority
JP
Japan
Prior art keywords
nonvolatile memory
memory
igfet
fets
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8043177A
Other languages
Japanese (ja)
Other versions
JPS578553B2 (en
Inventor
Yukimasa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8043177A priority Critical patent/JPS5416138A/en
Publication of JPS5416138A publication Critical patent/JPS5416138A/en
Publication of JPS578553B2 publication Critical patent/JPS578553B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To realize a nonvolatile semiconductor memory in which selective rewriting is made possible, by constituting a non volatile memory by connecting the source or drain of an IGFET to an injected-voltage application terminal and by combining the 2md and 3rd FETs with the memory.
JP8043177A 1977-07-07 1977-07-07 Nonvolatile memory Granted JPS5416138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8043177A JPS5416138A (en) 1977-07-07 1977-07-07 Nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8043177A JPS5416138A (en) 1977-07-07 1977-07-07 Nonvolatile memory

Publications (2)

Publication Number Publication Date
JPS5416138A true JPS5416138A (en) 1979-02-06
JPS578553B2 JPS578553B2 (en) 1982-02-17

Family

ID=13718071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8043177A Granted JPS5416138A (en) 1977-07-07 1977-07-07 Nonvolatile memory

Country Status (1)

Country Link
JP (1) JPS5416138A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686558A (en) * 1982-09-15 1987-08-11 Itt Industries, Inc. CMOS memory cell having an electrically floating storage gate
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6152257U (en) * 1984-09-11 1986-04-08
JPS63141443U (en) * 1987-03-09 1988-09-19

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686558A (en) * 1982-09-15 1987-08-11 Itt Industries, Inc. CMOS memory cell having an electrically floating storage gate
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
JPS578553B2 (en) 1982-02-17

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