JPS54152940A - Data correction control system - Google Patents

Data correction control system

Info

Publication number
JPS54152940A
JPS54152940A JP6110078A JP6110078A JPS54152940A JP S54152940 A JPS54152940 A JP S54152940A JP 6110078 A JP6110078 A JP 6110078A JP 6110078 A JP6110078 A JP 6110078A JP S54152940 A JPS54152940 A JP S54152940A
Authority
JP
Japan
Prior art keywords
error
counter
data
byte
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6110078A
Other languages
Japanese (ja)
Inventor
Ryosuke Toyohara
Hisaharu Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6110078A priority Critical patent/JPS54152940A/en
Publication of JPS54152940A publication Critical patent/JPS54152940A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To make it possible to correct data even if a controller has not any large buffer memory, by detecting a read error and then by finding and atoring the error position and error pattern by error correction code ECC.
CONSTITUTION: When data which can be corrected are detected by data part R1D of record 1, the position relative to an error byte and the error pattern are computed by the content of ECC of R1D, and the position relative to the error byte is founed on reference to the content of ECC generator 19 and stored in error byte counter 7. The error pattern, on the other hand, is stored in error-pattern shift register 13. Next, the controller positions the read head to R1D and sets the data length of R1D to data-length counter 6, thereby transferring data of R1D. At every byte time, counter 6 has its content subtracted by the output of counter 5 until a value equal to that of counter 7, and then, FF 11 is set to drive register 13, thereby correcting the error byte.
COPYRIGHT: (C)1979,JPO&Japio
JP6110078A 1978-05-24 1978-05-24 Data correction control system Pending JPS54152940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6110078A JPS54152940A (en) 1978-05-24 1978-05-24 Data correction control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6110078A JPS54152940A (en) 1978-05-24 1978-05-24 Data correction control system

Publications (1)

Publication Number Publication Date
JPS54152940A true JPS54152940A (en) 1979-12-01

Family

ID=13161319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6110078A Pending JPS54152940A (en) 1978-05-24 1978-05-24 Data correction control system

Country Status (1)

Country Link
JP (1) JPS54152940A (en)

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