JPS54150052A - Diagnosis system - Google Patents

Abstract

PURPOSE: To ensure performance of measurement of the transfer capacity as well as the diagnosis of the error detector circuit by installing the means to vary the timing of the data writing and reading to the data transfer buffer device.

CONSTITUTION: When the data is transferred, data transfer request signal SVI is sent to channel device 13 from the channel buffer (CB) control circuit. Thus, device 13 sends out the data to CB1 to turn on data transmission signal SVO. The CB control circuit confirms signal SVO and produces the transfer timing signal to transmits it to gate 7 and 10. Thus, signal SVO is turned off. Then device 13 confirms the OFF of SVI and turns off SVO to complete transfer of one data. At the diagnosis time, the timing delay setting value is changed freely to be set to register 15, and thus the transfer timing can be changed freely. As a result, the data transfer timing can be varied between device 13 and CB1 to ensure performance the measurement of the transfer capacity as well as the diagnosis for the adaptability decision of the decision of the decision circuit 6 for detection of the overrun.

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