JPS5473534A - Inter-system connecting system - Google Patents

Inter-system connecting system

Info

Publication number
JPS5473534A
JPS5473534A JP14087277A JP14087277A JPS5473534A JP S5473534 A JPS5473534 A JP S5473534A JP 14087277 A JP14087277 A JP 14087277A JP 14087277 A JP14087277 A JP 14087277A JP S5473534 A JPS5473534 A JP S5473534A
Authority
JP
Japan
Prior art keywords
data
inter
sent
buffer memory
block buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14087277A
Other languages
Japanese (ja)
Inventor
Hiroshi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14087277A priority Critical patent/JPS5473534A/en
Publication of JPS5473534A publication Critical patent/JPS5473534A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To enhance the data transfer rate by providing the block buffer memory within the inter-channel connecting device and securing the data transfer to the block buffer memory for both the data transmitter and receiver sides regardless of the remote side to each other.
CONSTITUTION: The system transmitter side transmits the write command to inter-channel connecting device 1. If block buffer memory 6 is idle, the data is transferred to memory 6 from system A irrespective of system B. An interruption is caused to system B at the end of the data transfer, and the channel end is sent to system A. With this interruption, system B transmits the read commend to unit 1 and transfers the data within memory 6 to system B. With the end of the transfer, both the channel end and the device end are sent to system B, and also the device end is sent to system A.
COPYRIGHT: (C)1979,JPO&Japio
JP14087277A 1977-11-24 1977-11-24 Inter-system connecting system Pending JPS5473534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14087277A JPS5473534A (en) 1977-11-24 1977-11-24 Inter-system connecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14087277A JPS5473534A (en) 1977-11-24 1977-11-24 Inter-system connecting system

Publications (1)

Publication Number Publication Date
JPS5473534A true JPS5473534A (en) 1979-06-12

Family

ID=15278710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14087277A Pending JPS5473534A (en) 1977-11-24 1977-11-24 Inter-system connecting system

Country Status (1)

Country Link
JP (1) JPS5473534A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01134648A (en) * 1987-11-20 1989-05-26 Yokogawa Electric Corp Method for communication between computers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01134648A (en) * 1987-11-20 1989-05-26 Yokogawa Electric Corp Method for communication between computers

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