JPS54149454A - Preset method - Google Patents

Preset method

Info

Publication number
JPS54149454A
JPS54149454A JP5840578A JP5840578A JPS54149454A JP S54149454 A JPS54149454 A JP S54149454A JP 5840578 A JP5840578 A JP 5840578A JP 5840578 A JP5840578 A JP 5840578A JP S54149454 A JPS54149454 A JP S54149454A
Authority
JP
Japan
Prior art keywords
state
parallel
data
output terminals
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5840578A
Other languages
Japanese (ja)
Other versions
JPS5858857B2 (en
Inventor
Tomoaki Irimichi
Sukeichi Miki
Shuichi Ninomiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53058405A priority Critical patent/JPS5858857B2/en
Publication of JPS54149454A publication Critical patent/JPS54149454A/en
Publication of JPS5858857B2 publication Critical patent/JPS5858857B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the transient change state of a PLL loop to shorten the time for stability by switching the state to a high-output impedance state of contents of the shift register and a state where contents stored in the shift register are outputted.
CONSTITUTION: Capacitors 56 to 60 are inserted one by one between each of parallel output terminals of shift register 48, which has a series input terminal, parallel output terminals and a control input terminal and stores plural-bit data, and one common earth terminal. parallel output terminals of register 48 are connected to parallel preset input terminals of variable frequency divider 40, which has plural parallel preset input terminals, respectively. During the data input period to register 48, two-state parallel output terminals do not output data and take a high-output impedance state; and during the data no input peiod, two-state parallel output terminals take a state where data stored in register 48 is outputted.
COPYRIGHT: (C)1979,JPO&Japio
JP53058405A 1978-05-16 1978-05-16 Preset method Expired JPS5858857B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53058405A JPS5858857B2 (en) 1978-05-16 1978-05-16 Preset method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53058405A JPS5858857B2 (en) 1978-05-16 1978-05-16 Preset method

Publications (2)

Publication Number Publication Date
JPS54149454A true JPS54149454A (en) 1979-11-22
JPS5858857B2 JPS5858857B2 (en) 1983-12-27

Family

ID=13083444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53058405A Expired JPS5858857B2 (en) 1978-05-16 1978-05-16 Preset method

Country Status (1)

Country Link
JP (1) JPS5858857B2 (en)

Also Published As

Publication number Publication date
JPS5858857B2 (en) 1983-12-27

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