JPS54148324A - Display system for electronic computer - Google Patents

Display system for electronic computer

Info

Publication number
JPS54148324A
JPS54148324A JP5689878A JP5689878A JPS54148324A JP S54148324 A JPS54148324 A JP S54148324A JP 5689878 A JP5689878 A JP 5689878A JP 5689878 A JP5689878 A JP 5689878A JP S54148324 A JPS54148324 A JP S54148324A
Authority
JP
Japan
Prior art keywords
written
order
circuit
memory
deciding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5689878A
Other languages
Japanese (ja)
Inventor
Masuaki Morino
Yoshiyuki Fujikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5689878A priority Critical patent/JPS54148324A/en
Publication of JPS54148324A publication Critical patent/JPS54148324A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To realize simplification of the device by deciding whether or not the order is written into the address of the memory into which the next key input order is written, displaying the flashing symbol when the order is written and at the same time designating and displaying the step to be written.
CONSTITUTION: The key order supplied from key unit KU are displayed continuously at display unit DSP in the symbols of alphabet letters, figures and others. In such computer, the CPU which reads out the contents of memory M and carries out them is provided along with buffer register BR which holds the contents of M by the address designation of the CPU. In addition, coincidence deciding circuit EJ which decides whether or not the order is written into memory M into which the next key input is to be written is installed along with code signal generator circuit SSG which generates the signal to display the cursor when no order is written. Thus, the output of circuit SSG is controlled by deciding circuit ZJ when the order is already written, and the symbol of the order is displayed with flashing through digit signal generator circuit TD1.
COPYRIGHT: (C)1979,JPO&Japio
JP5689878A 1978-05-13 1978-05-13 Display system for electronic computer Pending JPS54148324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5689878A JPS54148324A (en) 1978-05-13 1978-05-13 Display system for electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5689878A JPS54148324A (en) 1978-05-13 1978-05-13 Display system for electronic computer

Publications (1)

Publication Number Publication Date
JPS54148324A true JPS54148324A (en) 1979-11-20

Family

ID=13040257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5689878A Pending JPS54148324A (en) 1978-05-13 1978-05-13 Display system for electronic computer

Country Status (1)

Country Link
JP (1) JPS54148324A (en)

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