JPS54134962A - Generating circuit for dual-frequency signal - Google Patents

Generating circuit for dual-frequency signal

Info

Publication number
JPS54134962A
JPS54134962A JP4359378A JP4359378A JPS54134962A JP S54134962 A JPS54134962 A JP S54134962A JP 4359378 A JP4359378 A JP 4359378A JP 4359378 A JP4359378 A JP 4359378A JP S54134962 A JPS54134962 A JP S54134962A
Authority
JP
Japan
Prior art keywords
voltage
taps
resistor
dual
frequency signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4359378A
Other languages
Japanese (ja)
Inventor
Akira Yugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4359378A priority Critical patent/JPS54134962A/en
Publication of JPS54134962A publication Critical patent/JPS54134962A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a dual-frequency signal generating circuit of the miniaturized circuit constitution with its temperature dependency made small, by providing a common D/A converter.
CONSTITUTION: As for the resistance network constituting the D/A converter, taps whose number is equivalent to a ratio between a voltage needed as the maximum voltage and the minimum decomposed voltage are led out on both the side of a resistor at uniform intervals from the middle point of the resistor, and a voltage covering a range from the maximum voltage to the minimum voltage of a sine wave is divided uniformly on the time axis to select taps equivalent to respective division points from those taps; and the drain of the metal oxide film semiconductor switch (MOS switch) is connected to the taps and its source is connected to one side of the resistor in common, thereby obtaining output terminals 17 and 18. To the gate of the MOS switch, clock signals 15 and 16 are applied by way of gate selector circuits 10 and 11 and independent desirable output sine waves can be obtained from output terminals 17 and 18.
COPYRIGHT: (C)1979,JPO&Japio
JP4359378A 1978-04-12 1978-04-12 Generating circuit for dual-frequency signal Pending JPS54134962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4359378A JPS54134962A (en) 1978-04-12 1978-04-12 Generating circuit for dual-frequency signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4359378A JPS54134962A (en) 1978-04-12 1978-04-12 Generating circuit for dual-frequency signal

Publications (1)

Publication Number Publication Date
JPS54134962A true JPS54134962A (en) 1979-10-19

Family

ID=12668087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4359378A Pending JPS54134962A (en) 1978-04-12 1978-04-12 Generating circuit for dual-frequency signal

Country Status (1)

Country Link
JP (1) JPS54134962A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0720745U (en) * 1994-06-09 1995-04-11 財団法人工業技術研究院 Dual Tone Multi Frequency Generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0720745U (en) * 1994-06-09 1995-04-11 財団法人工業技術研究院 Dual Tone Multi Frequency Generator

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