JPS54130820A - Modulation system - Google Patents

Modulation system

Info

Publication number
JPS54130820A
JPS54130820A JP3955778A JP3955778A JPS54130820A JP S54130820 A JPS54130820 A JP S54130820A JP 3955778 A JP3955778 A JP 3955778A JP 3955778 A JP3955778 A JP 3955778A JP S54130820 A JPS54130820 A JP S54130820A
Authority
JP
Japan
Prior art keywords
circuit
signal
synchronizing
level
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3955778A
Other languages
Japanese (ja)
Inventor
Masao Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3955778A priority Critical patent/JPS54130820A/en
Publication of JPS54130820A publication Critical patent/JPS54130820A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a modulation system where a signal level can be lowered without suppressing required information included in signals by suppressing previously most synchronizing signals.
CONSTITUTION: The signal inputted to input terminal 1 is branched in two directions after the heading of synchronizing signals is clamped by peak clamper 201, and branched one is inputted to clipper 203, which clips the synchronizing part, after delayed through delay line 202. The other is supplied to synchronizing separation circuit 206 after applied to LPF 205 to remove color carrier components, and one output of circuit 206 is applied to synchronous level detector 207 to detect the synchronous level, and simultaneously, this level is converted to a corresponding DC signal and is transmitted to circuit 203 through gate circuit 209 as a clip level. Then, the other output of circuit 206 is applied to monostable multivibrator 210 to generate a signal slightly wider than the synchronizing signal which controls circuit 209. Then, the output of circuit 203 is applied to modulator 204, thereby modulating signals.
COPYRIGHT: (C)1979,JPO&Japio
JP3955778A 1978-04-03 1978-04-03 Modulation system Pending JPS54130820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3955778A JPS54130820A (en) 1978-04-03 1978-04-03 Modulation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3955778A JPS54130820A (en) 1978-04-03 1978-04-03 Modulation system

Publications (1)

Publication Number Publication Date
JPS54130820A true JPS54130820A (en) 1979-10-11

Family

ID=12556362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3955778A Pending JPS54130820A (en) 1978-04-03 1978-04-03 Modulation system

Country Status (1)

Country Link
JP (1) JPS54130820A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0381313A2 (en) * 1989-01-28 1990-08-08 The Marconi Company Limited Television transmitter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0381313A2 (en) * 1989-01-28 1990-08-08 The Marconi Company Limited Television transmitter

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