JPS54128655A - Oscillator for parallel redundancy - Google Patents
Oscillator for parallel redundancyInfo
- Publication number
- JPS54128655A JPS54128655A JP3706178A JP3706178A JPS54128655A JP S54128655 A JPS54128655 A JP S54128655A JP 3706178 A JP3706178 A JP 3706178A JP 3706178 A JP3706178 A JP 3706178A JP S54128655 A JPS54128655 A JP S54128655A
- Authority
- JP
- Japan
- Prior art keywords
- reclosing
- oscillation circuit
- oscillator
- switch
- operating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 abstract 4
- 230000001360 synchronised effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To enable to disconnect and reclosing of arbitrary oscillator while operating the invertor, by constituting the part contributing to the disconnection and reclosing with the switch and timer. CONSTITUTION:The oscillation circuit 1B consists of the oscillator 11, frequency divider 12, monostable multivibrator 13, line driver 16 feeding the output to the common bus, line receiver 17 receiving the pulse on the common bus, and monostable multivibrator 14. When disconnecting the oscillation circuit 1B, after disconnecting the switches 105A and 105B, the switch 104 is opened. Since the pulse of frequency standard is fed from the oscillation circuit 2B, disconnection is enabled while operating the invertors 1 to 3. Further, in reclosing the oscillation circuit 1B, first the switch 104 is closed and the power supply 31 is connected to the buffer circuit 101. After a given time T41, when the switches 105A and B are closed, the output of the timer 102 changes from 0 to 1 after a given time T42 to open the AND circuit 13. Since the frequency divider 12 is compulsively synchronized with the signal (a), the reclosing is possible while operating the inverters 1 to 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53037061A JPS59177B2 (en) | 1978-03-30 | 1978-03-30 | Parallel redundant oscillator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53037061A JPS59177B2 (en) | 1978-03-30 | 1978-03-30 | Parallel redundant oscillator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54128655A true JPS54128655A (en) | 1979-10-05 |
JPS59177B2 JPS59177B2 (en) | 1984-01-05 |
Family
ID=12487034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53037061A Expired JPS59177B2 (en) | 1978-03-30 | 1978-03-30 | Parallel redundant oscillator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59177B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6412571U (en) * | 1987-07-10 | 1989-01-23 |
-
1978
- 1978-03-30 JP JP53037061A patent/JPS59177B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS59177B2 (en) | 1984-01-05 |
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