JPS54127643A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS54127643A
JPS54127643A JP3518178A JP3518178A JPS54127643A JP S54127643 A JPS54127643 A JP S54127643A JP 3518178 A JP3518178 A JP 3518178A JP 3518178 A JP3518178 A JP 3518178A JP S54127643 A JPS54127643 A JP S54127643A
Authority
JP
Japan
Prior art keywords
interface
data transfer
dialogue
data
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3518178A
Other languages
Japanese (ja)
Inventor
Shuji Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3518178A priority Critical patent/JPS54127643A/en
Publication of JPS54127643A publication Critical patent/JPS54127643A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To carry out the data transfer of the different interfaces via the adaptor device performing the dialogue in duplication.
CONSTITUTION: The interruption given from interface 2 at the side of input/output device IO is decided at gate 91 and 92, and the transfer mode is memorized in FF93 and 94 each. The output of FF93 or 94 is delivered via gate 95 and then interrupted into interface 1 of the CPU side. While the END signal is delivered when the dialogue completes to be memorized in FF96 the data signal of interface 1 is lost. Then the data is held at the bus line via gate 97. When the END signal is received at FF98 and the dialogue comes to end also at interface 2, memory 96 is reset to complete the data transfer. Thus, the functions are shared for the firmware and the hardware, and the priority if given to the data transfer via the hardware to carry out the data transfer dialogue in duplication for the different interfaces. As a result, the IO of the different bus interface can be controlled.
COPYRIGHT: (C)1979,JPO&Japio
JP3518178A 1978-03-27 1978-03-27 Data transfer system Pending JPS54127643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3518178A JPS54127643A (en) 1978-03-27 1978-03-27 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3518178A JPS54127643A (en) 1978-03-27 1978-03-27 Data transfer system

Publications (1)

Publication Number Publication Date
JPS54127643A true JPS54127643A (en) 1979-10-03

Family

ID=12434671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3518178A Pending JPS54127643A (en) 1978-03-27 1978-03-27 Data transfer system

Country Status (1)

Country Link
JP (1) JPS54127643A (en)

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