JPS54126437A - Program control method - Google Patents

Program control method

Info

Publication number
JPS54126437A
JPS54126437A JP3447678A JP3447678A JPS54126437A JP S54126437 A JPS54126437 A JP S54126437A JP 3447678 A JP3447678 A JP 3447678A JP 3447678 A JP3447678 A JP 3447678A JP S54126437 A JPS54126437 A JP S54126437A
Authority
JP
Japan
Prior art keywords
circuit
program
instruction
return
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3447678A
Other languages
Japanese (ja)
Inventor
Akira Nagano
Kazuaki Urasaki
Kenji Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP3447678A priority Critical patent/JPS54126437A/en
Publication of JPS54126437A publication Critical patent/JPS54126437A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the number of program steps by programming the next step return instruction when the control is returned from subroutine SR or interrupt routine IR to main routine MR.
CONSTITUTION: Program unit 3 including ROM is addressed by program counter 2 which is controlled by program control circuit 1. Instructions from unit 3 are decoded by instruction decoder 4 and are given to circuit 1, etc. Instruction SKA1 which commands skip if the first bit of accumulator 8 in decoder 4 is "1" is given to decision circuit 7, and circuit 7 outputs "1" or "0" according to contents of the first bit of accumulator 8 and gives it to decoder 4. When instruction NXTRTN which commands return in the next step is decoded, it is delayed in delay circuit 5 by one program step and is outputted. The output of circuit 5 is given to circuit 1 through gate 6 together with normal return instruction RTN. As a result, the number of return program steps can be reduced.
COPYRIGHT: (C)1979,JPO&Japio
JP3447678A 1978-03-24 1978-03-24 Program control method Pending JPS54126437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3447678A JPS54126437A (en) 1978-03-24 1978-03-24 Program control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3447678A JPS54126437A (en) 1978-03-24 1978-03-24 Program control method

Publications (1)

Publication Number Publication Date
JPS54126437A true JPS54126437A (en) 1979-10-01

Family

ID=12415296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3447678A Pending JPS54126437A (en) 1978-03-24 1978-03-24 Program control method

Country Status (1)

Country Link
JP (1) JPS54126437A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161749A (en) * 1974-11-26 1976-05-28 Fujitsu Ltd Deetashorisochino shoriringuseigyohoshiki
JPS51147143A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Micro program control mechanism

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161749A (en) * 1974-11-26 1976-05-28 Fujitsu Ltd Deetashorisochino shoriringuseigyohoshiki
JPS51147143A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Micro program control mechanism

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