JPS54122927A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS54122927A
JPS54122927A JP3077178A JP3077178A JPS54122927A JP S54122927 A JPS54122927 A JP S54122927A JP 3077178 A JP3077178 A JP 3077178A JP 3077178 A JP3077178 A JP 3077178A JP S54122927 A JPS54122927 A JP S54122927A
Authority
JP
Japan
Prior art keywords
circuit
board
bias
terminal
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3077178A
Other languages
Japanese (ja)
Inventor
Tokiaki Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3077178A priority Critical patent/JPS54122927A/en
Publication of JPS54122927A publication Critical patent/JPS54122927A/en
Pending legal-status Critical Current

Links

Landscapes

  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Electronic Switches (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To enable to limit the flowing of positive power supply current, by restricting the application of the clock synchronizing signal to the board with the clock input control circuit through the reception of the output when the interruption of bias to the board is detected.
CONSTITUTION: The integrated circuit 1 including the clock synchronizing N channel MOS circuit is provided with the terminal 2 to which a positive power supply is fed and the terminal 3 to which negative board bias is fed. The clock signal to the circuit 1 is fed to the terminal 4, and the clock input control circuit 6 is controlled with the output of the board bias interruption detection circuit 5. If the bias potential to the board bias terminal 3 is in failure such as interruption, the circuit 5 detects this and controls the circuit 6 so that the clock signal to the circuit 1 is inhibited or the intensity is reduced. Thus, the flowing of the positive power supply current can be limited.
COPYRIGHT: (C)1979,JPO&Japio
JP3077178A 1978-03-16 1978-03-16 Integrated circuit Pending JPS54122927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3077178A JPS54122927A (en) 1978-03-16 1978-03-16 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3077178A JPS54122927A (en) 1978-03-16 1978-03-16 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS54122927A true JPS54122927A (en) 1979-09-22

Family

ID=12312937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3077178A Pending JPS54122927A (en) 1978-03-16 1978-03-16 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS54122927A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60241323A (en) * 1984-05-16 1985-11-30 Seiko Epson Corp Output protective circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60241323A (en) * 1984-05-16 1985-11-30 Seiko Epson Corp Output protective circuit

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