JPS54115026A - Signal read-in system to microprocessor - Google Patents

Signal read-in system to microprocessor

Info

Publication number
JPS54115026A
JPS54115026A JP2387378A JP2387378A JPS54115026A JP S54115026 A JPS54115026 A JP S54115026A JP 2387378 A JP2387378 A JP 2387378A JP 2387378 A JP2387378 A JP 2387378A JP S54115026 A JPS54115026 A JP S54115026A
Authority
JP
Japan
Prior art keywords
led
fet
input terminal
mpu
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2387378A
Other languages
Japanese (ja)
Inventor
Masaaki Maekawa
Takashi Nishida
Susumu Genban
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2387378A priority Critical patent/JPS54115026A/en
Publication of JPS54115026A publication Critical patent/JPS54115026A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable to effective read-in only with one input terminal, by connecting a plurality of FET's in parallel with one input terminal provided with a microprocessor, and by connecting the FET to a plurality of LED's via resistors through correspondence.
CONSTITUTION: One input terminal is provided for the microprocesser MPU controlling input and output signal, and this is connected to the source or drsin of FET elements SW1 to SWn with a plurality sets in parallel connection operated as analog switches. Further, a plurality of output terminals a1 to an of the processor MPU are connected to the drain or source of the elements SW1 to SWn, and the gate of SW1 to SWn is connected to the output terminals O1 to On of the information unit consisting of the series circuit of resistor R1 and LED1,R2 and LED2,Rn and LEDn. With this constitution, a voltage of around logic level is fed to the processor MPU, and the current to LED1 to LEDn is adjusted with resistors R1 to Rn, and the signal from the external unit is read in the processor MPU.
COPYRIGHT: (C)1979,JPO&Japio
JP2387378A 1978-02-28 1978-02-28 Signal read-in system to microprocessor Pending JPS54115026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2387378A JPS54115026A (en) 1978-02-28 1978-02-28 Signal read-in system to microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2387378A JPS54115026A (en) 1978-02-28 1978-02-28 Signal read-in system to microprocessor

Publications (1)

Publication Number Publication Date
JPS54115026A true JPS54115026A (en) 1979-09-07

Family

ID=12122557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2387378A Pending JPS54115026A (en) 1978-02-28 1978-02-28 Signal read-in system to microprocessor

Country Status (1)

Country Link
JP (1) JPS54115026A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS524748A (en) * 1975-06-27 1977-01-14 Western Electric Co Selffcheck reading and writing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS524748A (en) * 1975-06-27 1977-01-14 Western Electric Co Selffcheck reading and writing circuit

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