JPS54118742A - Decoder circuit - Google Patents

Decoder circuit

Info

Publication number
JPS54118742A
JPS54118742A JP2639178A JP2639178A JPS54118742A JP S54118742 A JPS54118742 A JP S54118742A JP 2639178 A JP2639178 A JP 2639178A JP 2639178 A JP2639178 A JP 2639178A JP S54118742 A JPS54118742 A JP S54118742A
Authority
JP
Japan
Prior art keywords
level
switched
segment
signal
display segments
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2639178A
Other languages
Japanese (ja)
Other versions
JPS648344B2 (en
Inventor
Yasushi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2639178A priority Critical patent/JPS54118742A/en
Publication of JPS54118742A publication Critical patent/JPS54118742A/en
Publication of JPS648344B2 publication Critical patent/JPS648344B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To decrease the number of the element for the decoder circuit in which the 1st and 2nd MOS element groups are connected in series by setting both power sources of each segment signal output circuit at the same level when all display segments are switched on and off respectively.
CONSTITUTION: N-channel MOS element groups 111 and 112 plus P-channel MOS element groups 121 and 122 are connected in series to segment signal output circuits 101 and 102. When the segment signal is at the H level, the element segment is switched on but switched off with the L level respectively. Signal Son and Soff are at the L level, segment signal Seg1 and Seg2 become the H level with all display segments switched on. While both signals Soff and Son are at the H level, signal Seg1 and Seg2 become the L level with all display segments switched off. In such circuit constitution, four elements can be reduced with each segment to be applied suitably to the integrated circuit.
COPYRIGHT: (C)1979,JPO&Japio
JP2639178A 1978-03-08 1978-03-08 Decoder circuit Granted JPS54118742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2639178A JPS54118742A (en) 1978-03-08 1978-03-08 Decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2639178A JPS54118742A (en) 1978-03-08 1978-03-08 Decoder circuit

Publications (2)

Publication Number Publication Date
JPS54118742A true JPS54118742A (en) 1979-09-14
JPS648344B2 JPS648344B2 (en) 1989-02-13

Family

ID=12192231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2639178A Granted JPS54118742A (en) 1978-03-08 1978-03-08 Decoder circuit

Country Status (1)

Country Link
JP (1) JPS54118742A (en)

Also Published As

Publication number Publication date
JPS648344B2 (en) 1989-02-13

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