JPS54109739A - Free address decision method for microprocessor - Google Patents

Free address decision method for microprocessor

Info

Publication number
JPS54109739A
JPS54109739A JP1651278A JP1651278A JPS54109739A JP S54109739 A JPS54109739 A JP S54109739A JP 1651278 A JP1651278 A JP 1651278A JP 1651278 A JP1651278 A JP 1651278A JP S54109739 A JPS54109739 A JP S54109739A
Authority
JP
Japan
Prior art keywords
program
address
converter
alteration
rom2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1651278A
Other languages
Japanese (ja)
Inventor
Takeshi Onuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1651278A priority Critical patent/JPS54109739A/en
Publication of JPS54109739A publication Critical patent/JPS54109739A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure a facilitated alteration of the program with no hardware change of the program counter via the converting function for the program alteration between the additional logic part and the address converter connected onto the data address bus.
CONSTITUTION: Microprocessor 1 is provided to perform the execution and decoding of the order, along with memory device ROM2 which contains program part 6 to carry out the control for the subject to be controlled plus additional and alteration program part 7. Furthermore, address converter 3 is provided to supply the input information of the memory address bus and then to deliver the corresponding address information plus the switch signal of address selector 4. Thus, the address information of ROM2 is selected via selector 4 when no output 5 exists in converter 3 to execute the program of part 6. And when the data on bus 8 is in agreement with the output conditions deciding the output conditions of converter 3, the output information of converter 3 is selected at ROM2. Thus, the additional and alteration orders of part 7 are taken into processor 1.
COPYRIGHT: (C)1979,JPO&Japio
JP1651278A 1978-02-17 1978-02-17 Free address decision method for microprocessor Pending JPS54109739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1651278A JPS54109739A (en) 1978-02-17 1978-02-17 Free address decision method for microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1651278A JPS54109739A (en) 1978-02-17 1978-02-17 Free address decision method for microprocessor

Publications (1)

Publication Number Publication Date
JPS54109739A true JPS54109739A (en) 1979-08-28

Family

ID=11918315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1651278A Pending JPS54109739A (en) 1978-02-17 1978-02-17 Free address decision method for microprocessor

Country Status (1)

Country Link
JP (1) JPS54109739A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106399U (en) * 1985-12-20 1987-07-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106399U (en) * 1985-12-20 1987-07-07

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