JPS54109715A - Signal piling system for rz-binary ami code - Google Patents

Signal piling system for rz-binary ami code

Info

Publication number
JPS54109715A
JPS54109715A JP1590878A JP1590878A JPS54109715A JP S54109715 A JPS54109715 A JP S54109715A JP 1590878 A JP1590878 A JP 1590878A JP 1590878 A JP1590878 A JP 1590878A JP S54109715 A JPS54109715 A JP S54109715A
Authority
JP
Japan
Prior art keywords
signal
binary
logical product
code
secured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1590878A
Other languages
Japanese (ja)
Other versions
JPS581579B2 (en
Inventor
Yukio Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53015908A priority Critical patent/JPS581579B2/en
Publication of JPS54109715A publication Critical patent/JPS54109715A/en
Publication of JPS581579B2 publication Critical patent/JPS581579B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To reduce the average duty ratio of the pulse by having the pile transmission through lacking of the head pulse of the RZ-binary AMI code in accordance with various kinds of piling signals. CONSTITUTION:Code b given from binary AMI signal generator 1 is converted into RZ-binary AMI code c. Code c along with signal d sent from piling signal generator 3 are supplied to FF4, and the logical product is obtained through logical product circuit 5. Thus, signal e which lacks the first pulse is obtained. Signal e is then transmitted to the reception side, and the exclusive logic is secured between the signal which is delayed by 1/2 bit to obtain signal i. Then the logical product is obtained between signal i and synchronous signal j to obtain signal k. And the logical product is secured between signal m from timing extracting circuit 14 and signal l obtained by delaying signal k by 2 bits, thus obtaining signal n. On the other hand, the logical sum is secured between output k of logical product 12 and the signal sent from delay circuit 18 to obtain signal o with its error corrected.
JP53015908A 1978-02-16 1978-02-16 RZ↓-binary AMI code signal superposition method Expired JPS581579B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53015908A JPS581579B2 (en) 1978-02-16 1978-02-16 RZ↓-binary AMI code signal superposition method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53015908A JPS581579B2 (en) 1978-02-16 1978-02-16 RZ↓-binary AMI code signal superposition method

Publications (2)

Publication Number Publication Date
JPS54109715A true JPS54109715A (en) 1979-08-28
JPS581579B2 JPS581579B2 (en) 1983-01-12

Family

ID=11901862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53015908A Expired JPS581579B2 (en) 1978-02-16 1978-02-16 RZ↓-binary AMI code signal superposition method

Country Status (1)

Country Link
JP (1) JPS581579B2 (en)

Also Published As

Publication number Publication date
JPS581579B2 (en) 1983-01-12

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