JPS54106142A - Data processor - Google Patents
Data processorInfo
- Publication number
- JPS54106142A JPS54106142A JP1384178A JP1384178A JPS54106142A JP S54106142 A JPS54106142 A JP S54106142A JP 1384178 A JP1384178 A JP 1384178A JP 1384178 A JP1384178 A JP 1384178A JP S54106142 A JPS54106142 A JP S54106142A
- Authority
- JP
- Japan
- Prior art keywords
- address
- given
- stuck
- sequence
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Executing Machine-Instructions (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE: To facilitate an easy error detection and thus to obtain a data processor which is useful for debug by providing the stuck mechanism for the specific address generating function at the deepest level of stuck register STR which functions as the address shunt area.
CONSTITUTION: Program counter PC1 connected to memory element 6 which is controlled by address bus 5 and dada bus 4 makes address A1 under execution shunt to address STR2 when the interruption process, the subroutine process and others are carried out. In case many kinds of these processes are carried out, the push-down is given to the deeper stucks in sequence to be filled by A1WAn, and then A1 is overflown to disappear when the subroutine process is given for N + 1 circuit. Here, if the pop-up is given, the resetting is given to PC1 from An+1. At the same time, specified address P is written into the deepest register through writing mechanism 3. The address which is poped up in sequence and reset at n + 1st time is specified address P, thus ensuring the detection of the error occurrence caused by the stuck overflow.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1384178A JPS54106142A (en) | 1978-02-08 | 1978-02-08 | Data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1384178A JPS54106142A (en) | 1978-02-08 | 1978-02-08 | Data processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54106142A true JPS54106142A (en) | 1979-08-20 |
JPS6124730B2 JPS6124730B2 (en) | 1986-06-12 |
Family
ID=11844493
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1384178A Granted JPS54106142A (en) | 1978-02-08 | 1978-02-08 | Data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54106142A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59111542A (en) * | 1982-12-03 | 1984-06-27 | ハネイウエル・インフオメ−シヨン・システムス・インコ−ポレ−テツド | Program counter stack method and nested subroutine and instruction apparatus |
JPS59154557A (en) * | 1983-02-24 | 1984-09-03 | Toshiba Corp | Detection system for program runaway |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53140947A (en) * | 1977-05-16 | 1978-12-08 | Hitachi Ltd | Logging system for communication control unit |
-
1978
- 1978-02-08 JP JP1384178A patent/JPS54106142A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53140947A (en) * | 1977-05-16 | 1978-12-08 | Hitachi Ltd | Logging system for communication control unit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59111542A (en) * | 1982-12-03 | 1984-06-27 | ハネイウエル・インフオメ−シヨン・システムス・インコ−ポレ−テツド | Program counter stack method and nested subroutine and instruction apparatus |
JPS59154557A (en) * | 1983-02-24 | 1984-09-03 | Toshiba Corp | Detection system for program runaway |
Also Published As
Publication number | Publication date |
---|---|
JPS6124730B2 (en) | 1986-06-12 |
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