JPS54105940A - Transfer system - Google Patents

Transfer system

Info

Publication number
JPS54105940A
JPS54105940A JP1259178A JP1259178A JPS54105940A JP S54105940 A JPS54105940 A JP S54105940A JP 1259178 A JP1259178 A JP 1259178A JP 1259178 A JP1259178 A JP 1259178A JP S54105940 A JPS54105940 A JP S54105940A
Authority
JP
Japan
Prior art keywords
circuit
signal
bus
reply
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1259178A
Other languages
Japanese (ja)
Other versions
JPS614145B2 (en
Inventor
Masahiko Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1259178A priority Critical patent/JPS54105940A/en
Publication of JPS54105940A publication Critical patent/JPS54105940A/en
Publication of JPS614145B2 publication Critical patent/JPS614145B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To enhance both the process efficiency and the flexibility by memorizing plural number of the device name into each processor, and at the same time to increase the process velocity and the system reliability.
CONSTITUTION: Discrimination reply circuit 1 delivers coincidence signal 11 and supplies it to reply circuit 2 when the coincidence is obtained between many device names memorized in circuit 1 and the partner name on bus 10 and when the request cycle is secured on bus 10 combining the processor and the input/output device. Circuit 2 memorizes the names of the transmitter and the receiver on bus 10 when signal 11 is transmitted, and then starts the reply cycle to supply processor main body 3 effective signal 12 informing the request becomes effective when the approval signal is obtained from the device which had a request.
COPYRIGHT: (C)1979,JPO&Japio
JP1259178A 1978-02-07 1978-02-07 Transfer system Granted JPS54105940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1259178A JPS54105940A (en) 1978-02-07 1978-02-07 Transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1259178A JPS54105940A (en) 1978-02-07 1978-02-07 Transfer system

Publications (2)

Publication Number Publication Date
JPS54105940A true JPS54105940A (en) 1979-08-20
JPS614145B2 JPS614145B2 (en) 1986-02-07

Family

ID=11809583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1259178A Granted JPS54105940A (en) 1978-02-07 1978-02-07 Transfer system

Country Status (1)

Country Link
JP (1) JPS54105940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079452A (en) * 1983-10-06 1985-05-07 Oki Electric Ind Co Ltd Address assignment system for module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079452A (en) * 1983-10-06 1985-05-07 Oki Electric Ind Co Ltd Address assignment system for module
JPH0118463B2 (en) * 1983-10-06 1989-04-05 Oki Electric Ind Co Ltd

Also Published As

Publication number Publication date
JPS614145B2 (en) 1986-02-07

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