JPS54103616A - Clock pulse regenerating circuit - Google Patents

Clock pulse regenerating circuit

Info

Publication number
JPS54103616A
JPS54103616A JP1095678A JP1095678A JPS54103616A JP S54103616 A JPS54103616 A JP S54103616A JP 1095678 A JP1095678 A JP 1095678A JP 1095678 A JP1095678 A JP 1095678A JP S54103616 A JPS54103616 A JP S54103616A
Authority
JP
Japan
Prior art keywords
output
clock pulse
gate
filter
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1095678A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6117385B2 (enExample
Inventor
Gozo Kage
Ikuo Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1095678A priority Critical patent/JPS54103616A/ja
Publication of JPS54103616A publication Critical patent/JPS54103616A/ja
Publication of JPS6117385B2 publication Critical patent/JPS6117385B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP1095678A 1978-02-01 1978-02-01 Clock pulse regenerating circuit Granted JPS54103616A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1095678A JPS54103616A (en) 1978-02-01 1978-02-01 Clock pulse regenerating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1095678A JPS54103616A (en) 1978-02-01 1978-02-01 Clock pulse regenerating circuit

Publications (2)

Publication Number Publication Date
JPS54103616A true JPS54103616A (en) 1979-08-15
JPS6117385B2 JPS6117385B2 (enExample) 1986-05-07

Family

ID=11764632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1095678A Granted JPS54103616A (en) 1978-02-01 1978-02-01 Clock pulse regenerating circuit

Country Status (1)

Country Link
JP (1) JPS54103616A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010166404A (ja) * 2009-01-16 2010-07-29 Hitachi Ltd バースト受信回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010166404A (ja) * 2009-01-16 2010-07-29 Hitachi Ltd バースト受信回路

Also Published As

Publication number Publication date
JPS6117385B2 (enExample) 1986-05-07

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