JPS5292442A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS5292442A
JPS5292442A JP846576A JP846576A JPS5292442A JP S5292442 A JPS5292442 A JP S5292442A JP 846576 A JP846576 A JP 846576A JP 846576 A JP846576 A JP 846576A JP S5292442 A JPS5292442 A JP S5292442A
Authority
JP
Japan
Prior art keywords
memory circuit
information
write
enable
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP846576A
Other languages
Japanese (ja)
Inventor
Ichiro Ohigata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP846576A priority Critical patent/JPS5292442A/en
Publication of JPS5292442A publication Critical patent/JPS5292442A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To enable the write-in and non destructive readout of the information to the memory cell with three input information and to make the power consumption at the hold condition zero.
JP846576A 1976-01-30 1976-01-30 Memory circuit Pending JPS5292442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP846576A JPS5292442A (en) 1976-01-30 1976-01-30 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP846576A JPS5292442A (en) 1976-01-30 1976-01-30 Memory circuit

Publications (1)

Publication Number Publication Date
JPS5292442A true JPS5292442A (en) 1977-08-03

Family

ID=11693871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP846576A Pending JPS5292442A (en) 1976-01-30 1976-01-30 Memory circuit

Country Status (1)

Country Link
JP (1) JPS5292442A (en)

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