JPS5255337A - Refresh control system - Google Patents

Refresh control system

Info

Publication number
JPS5255337A
JPS5255337A JP50130462A JP13046275A JPS5255337A JP S5255337 A JPS5255337 A JP S5255337A JP 50130462 A JP50130462 A JP 50130462A JP 13046275 A JP13046275 A JP 13046275A JP S5255337 A JPS5255337 A JP S5255337A
Authority
JP
Japan
Prior art keywords
control system
refresh control
refresh
synchronization
secured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50130462A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5516350B2 (enExample
Inventor
Shinji Katono
Tsuneyo Chiba
Kiyoshi Umezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50130462A priority Critical patent/JPS5255337A/ja
Priority to US05/737,350 priority patent/US4158883A/en
Publication of JPS5255337A publication Critical patent/JPS5255337A/ja
Publication of JPS5516350B2 publication Critical patent/JPS5516350B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP50130462A 1975-10-31 1975-10-31 Refresh control system Granted JPS5255337A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP50130462A JPS5255337A (en) 1975-10-31 1975-10-31 Refresh control system
US05/737,350 US4158883A (en) 1975-10-31 1976-11-01 Refresh control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50130462A JPS5255337A (en) 1975-10-31 1975-10-31 Refresh control system

Publications (2)

Publication Number Publication Date
JPS5255337A true JPS5255337A (en) 1977-05-06
JPS5516350B2 JPS5516350B2 (enExample) 1980-05-01

Family

ID=15034807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50130462A Granted JPS5255337A (en) 1975-10-31 1975-10-31 Refresh control system

Country Status (2)

Country Link
US (1) US4158883A (enExample)
JP (1) JPS5255337A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5472928A (en) * 1977-11-24 1979-06-11 Hitachi Ltd Memory controller
JP2005258587A (ja) * 2004-03-09 2005-09-22 Nec Access Technica Ltd メモリ制御回路およびメモリ制御方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4316248A (en) * 1978-12-06 1982-02-16 Data General Corporation Memory refresh means including means for providing refresh addresses during power failures
US4249247A (en) * 1979-01-08 1981-02-03 Ncr Corporation Refresh system for dynamic RAM memory
FR2474227A1 (fr) * 1980-01-17 1981-07-24 Cii Honeywell Bull Procede de rafraichissement pour banc de memoire a circuit " mos " et sequenceur correspondant
US4556952A (en) * 1981-08-12 1985-12-03 International Business Machines Corporation Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
JPS58192148A (ja) * 1982-05-07 1983-11-09 Hitachi Ltd 演算処理装置
US4594656A (en) * 1982-06-14 1986-06-10 Moffett Richard C Memory refresh apparatus
US4723204A (en) * 1982-07-07 1988-02-02 Gte Automatic Electric Incorporated Dynamic RAM refresh circuit
US4593370A (en) * 1982-07-26 1986-06-03 Hayati Balkanli Environmental measuring and recording apparatus
JPS59140694A (ja) * 1983-01-31 1984-08-13 Sharp Corp ダイナミツクｒａｍのリフレツシユ方法
US4639858A (en) * 1983-07-05 1987-01-27 Honeywell Information Systems Inc. Apparatus and method for testing and verifying the refresh logic of dynamic MOS memories
JPS60113395A (ja) * 1983-11-25 1985-06-19 Hitachi Ltd メモリ制御回路
EP0164735A3 (en) * 1984-06-11 1988-11-09 Nec Corporation A microprocessor having a dynamic memory refresh circuit
US4754425A (en) * 1985-10-18 1988-06-28 Gte Communication Systems Corporation Dynamic random access memory refresh circuit selectively adapted to different clock frequencies
US4700330A (en) * 1985-10-30 1987-10-13 Digital Equipment Corporation Memory for a digital data processing system including circuit for controlling refresh operations during power-up and power-down conditions
US4837735A (en) * 1987-06-09 1989-06-06 Martin Marietta Energy Systems, Inc. Parallel machine architecture for production rule systems
US4884234A (en) * 1987-06-29 1989-11-28 Ncr Corporation Dynamic RAM refresh circuit with DMA access
KR960009960B1 (ko) * 1994-03-12 1996-07-25 금성일렉트론 주식회사 디램의 리프레쉬 콘트롤회로

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760379A (en) * 1971-12-29 1973-09-18 Honeywell Inf Systems Apparatus and method for memory refreshment control
US3800295A (en) * 1971-12-30 1974-03-26 Ibm Asynchronously operated memory system
US3810129A (en) * 1972-10-19 1974-05-07 Ibm Memory system restoration

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5472928A (en) * 1977-11-24 1979-06-11 Hitachi Ltd Memory controller
JP2005258587A (ja) * 2004-03-09 2005-09-22 Nec Access Technica Ltd メモリ制御回路およびメモリ制御方法

Also Published As

Publication number Publication date
JPS5516350B2 (enExample) 1980-05-01
US4158883A (en) 1979-06-19

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