JPS511082A - - Google Patents
Info
- Publication number
- JPS511082A JPS511082A JP50050840A JP5084075A JPS511082A JP S511082 A JPS511082 A JP S511082A JP 50050840 A JP50050840 A JP 50050840A JP 5084075 A JP5084075 A JP 5084075A JP S511082 A JPS511082 A JP S511082A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- C25F3/00—Electrolytic etching or polishing
- C25F3/02—Etching
- C25F3/12—Etching of semiconducting materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02307—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/911—Differential oxidation and etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US479321A US3919060A (en) | 1974-06-14 | 1974-06-14 | Method of fabricating semiconductor device embodying dielectric isolation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS511082A true JPS511082A (en, 2012) | 1976-01-07 |
Family
ID=23903534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50050840A Pending JPS511082A (en, 2012) | 1974-06-14 | 1975-04-28 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US3919060A (en, 2012) |
| JP (1) | JPS511082A (en, 2012) |
| DE (1) | DE2521568A1 (en, 2012) |
| FR (1) | FR2275027A1 (en, 2012) |
| IT (1) | IT1037478B (en, 2012) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61283132A (ja) * | 1985-06-10 | 1986-12-13 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路基板の製造方法 |
| US8727718B2 (en) | 2008-03-26 | 2014-05-20 | Man Diesel & Turbo Se | Turbine rotor for a gas turbine |
| CN112563143A (zh) * | 2019-09-25 | 2021-03-26 | 长鑫存储技术有限公司 | 半导体结构制造方法 |
Families Citing this family (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4006045A (en) * | 1974-10-21 | 1977-02-01 | International Business Machines Corporation | Method for producing high power semiconductor device using anodic treatment and enhanced diffusion |
| US3954523A (en) * | 1975-04-14 | 1976-05-04 | International Business Machines Corporation | Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation |
| US4542579A (en) * | 1975-06-30 | 1985-09-24 | International Business Machines Corporation | Method for forming aluminum oxide dielectric isolation in integrated circuits |
| US4056415A (en) * | 1975-08-04 | 1977-11-01 | International Telephone And Telegraph Corporation | Method for providing electrical isolating material in selected regions of a semiconductive material |
| US4016017A (en) * | 1975-11-28 | 1977-04-05 | International Business Machines Corporation | Integrated circuit isolation structure and method for producing the isolation structure |
| US4094057A (en) * | 1976-03-29 | 1978-06-13 | International Business Machines Corporation | Field effect transistor lost film fabrication process |
| US4028149A (en) * | 1976-06-30 | 1977-06-07 | Ibm Corporation | Process for forming monocrystalline silicon carbide on silicon substrates |
| US4057823A (en) * | 1976-07-02 | 1977-11-08 | International Business Machines Corporation | Porous silicon dioxide moisture sensor and method for manufacture of a moisture sensor |
| US4104090A (en) * | 1977-02-24 | 1978-08-01 | International Business Machines Corporation | Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation |
| US4111720A (en) * | 1977-03-31 | 1978-09-05 | International Business Machines Corporation | Method for forming a non-epitaxial bipolar integrated circuit |
| US4264382A (en) * | 1978-05-25 | 1981-04-28 | International Business Machines Corporation | Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions |
| US4180416A (en) * | 1978-09-27 | 1979-12-25 | International Business Machines Corporation | Thermal migration-porous silicon technique for forming deep dielectric isolation |
| GB2038548B (en) * | 1978-10-27 | 1983-03-23 | Nippon Telegraph & Telephone | Isolating semiconductor device by porous silicon oxide |
| FR2472268A1 (fr) * | 1979-12-21 | 1981-06-26 | Thomson Csf | Procede de formation de caisson dans des circuits integres |
| US4506283A (en) * | 1981-05-08 | 1985-03-19 | Rockwell International Corporation | Small area high value resistor with greatly reduced parasitic capacitance |
| US4380865A (en) * | 1981-11-13 | 1983-04-26 | Bell Telephone Laboratories, Incorporated | Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation |
| US4532700A (en) * | 1984-04-27 | 1985-08-06 | International Business Machines Corporation | Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer |
| US4628591A (en) * | 1984-10-31 | 1986-12-16 | Texas Instruments Incorporated | Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon |
| US4897698A (en) * | 1984-10-31 | 1990-01-30 | Texas Instruments Incorporated | Horizontal structure thin film transistor |
| US4627883A (en) * | 1985-04-01 | 1986-12-09 | Gte Laboratories Incorporated | Method of forming an isolated semiconductor structure |
| US4910165A (en) * | 1988-11-04 | 1990-03-20 | Ncr Corporation | Method for forming epitaxial silicon on insulator structures using oxidized porous silicon |
| US5023200A (en) * | 1988-11-22 | 1991-06-11 | The United States Of America As Represented By The United States Department Of Energy | Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies |
| US5583368A (en) * | 1994-08-11 | 1996-12-10 | International Business Machines Corporation | Stacked devices |
| DE19501838A1 (de) * | 1995-01-21 | 1996-07-25 | Telefunken Microelectron | Verfahren zum Herstellen von SOI-Strukturen |
| US5863826A (en) * | 1996-08-02 | 1999-01-26 | Micron Technology, Inc. | CMOS isolation utilizing enhanced oxidation of recessed porous silicon formed by light ion implantation |
| US6251470B1 (en) | 1997-10-09 | 2001-06-26 | Micron Technology, Inc. | Methods of forming insulating materials, and methods of forming insulating materials around a conductive component |
| US6858526B2 (en) * | 1998-07-14 | 2005-02-22 | Micron Technology, Inc. | Methods of forming materials between conductive electrical components, and insulating materials |
| US6333556B1 (en) | 1997-10-09 | 2001-12-25 | Micron Technology, Inc. | Insulating materials |
| DE19810825A1 (de) * | 1998-03-12 | 1999-09-16 | Siemens Ag | Integrierte elektronische Schaltungsanordnung und Verfahren zu ihrer Herstellung |
| JPH11260734A (ja) | 1998-03-12 | 1999-09-24 | Nec Corp | 半導体装置の製造方法 |
| GB9808052D0 (en) * | 1998-04-17 | 1998-06-17 | Secr Defence | Implants for administering substances and methods of producing implants |
| US6056868A (en) * | 1998-05-22 | 2000-05-02 | Cheah; Kok Wei | Rare earth doping of porous silicon |
| US5950094A (en) * | 1999-02-18 | 1999-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating fully dielectric isolated silicon (FDIS) |
| US6350679B1 (en) | 1999-08-03 | 2002-02-26 | Micron Technology, Inc. | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry |
| TW556311B (en) * | 2001-07-31 | 2003-10-01 | Infineon Technologies Ag | Method for filling trenches in integrated semiconductor circuits |
| DE10149139A1 (de) * | 2001-10-05 | 2003-04-24 | Bosch Gmbh Robert | Verfahren zum Erzeugen von Hohlräumen mit einer optisch transparenten Wandung |
| US7342293B2 (en) * | 2005-12-05 | 2008-03-11 | International Business Machines Corporation | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same |
| AU2010246067B2 (en) * | 2009-05-04 | 2016-07-07 | Eyepoint Pharmaceuticals Us, Inc. | Porous silicon drug-eluting particles |
| AU2011323524B2 (en) | 2010-11-01 | 2016-12-08 | Eyepoint Pharmaceuticals Us, Inc. | Bioerodible silicon-based devices for delivery of therapeutic agents |
| CA2904077A1 (en) | 2013-03-15 | 2014-09-25 | Psivida Us, Inc. | Bioerodible silicon-based compositions for delivery of therapeutic agents |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48102988A (en, 2012) * | 1972-04-07 | 1973-12-24 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3386865A (en) * | 1965-05-10 | 1968-06-04 | Ibm | Process of making planar semiconductor devices isolated by encapsulating oxide filled channels |
| US3640806A (en) * | 1970-01-05 | 1972-02-08 | Nippon Telegraph & Telephone | Semiconductor device and method of producing the same |
| US3661741A (en) * | 1970-10-07 | 1972-05-09 | Bell Telephone Labor Inc | Fabrication of integrated semiconductor devices by electrochemical etching |
| US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
-
1974
- 1974-06-14 US US479321A patent/US3919060A/en not_active Expired - Lifetime
-
1975
- 1975-04-21 IT IT22558/75A patent/IT1037478B/it active
- 1975-04-28 JP JP50050840A patent/JPS511082A/ja active Pending
- 1975-04-29 FR FR7514039A patent/FR2275027A1/fr active Granted
- 1975-05-15 DE DE19752521568 patent/DE2521568A1/de not_active Withdrawn
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48102988A (en, 2012) * | 1972-04-07 | 1973-12-24 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61283132A (ja) * | 1985-06-10 | 1986-12-13 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路基板の製造方法 |
| US8727718B2 (en) | 2008-03-26 | 2014-05-20 | Man Diesel & Turbo Se | Turbine rotor for a gas turbine |
| CN112563143A (zh) * | 2019-09-25 | 2021-03-26 | 长鑫存储技术有限公司 | 半导体结构制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2521568A1 (de) | 1976-01-02 |
| US3919060A (en) | 1975-11-11 |
| IT1037478B (it) | 1979-11-10 |
| FR2275027B1 (en, 2012) | 1977-07-08 |
| FR2275027A1 (fr) | 1976-01-09 |