JPS4932604B1 - - Google Patents

Info

Publication number
JPS4932604B1
JPS4932604B1 JP45035324A JP3532470A JPS4932604B1 JP S4932604 B1 JPS4932604 B1 JP S4932604B1 JP 45035324 A JP45035324 A JP 45035324A JP 3532470 A JP3532470 A JP 3532470A JP S4932604 B1 JPS4932604 B1 JP S4932604B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP45035324A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4932604B1 publication Critical patent/JPS4932604B1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
JP45035324A 1969-04-29 1970-04-24 Pending JPS4932604B1 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US82021169A 1969-04-29 1969-04-29

Publications (1)

Publication Number Publication Date
JPS4932604B1 true JPS4932604B1 (ja) 1974-08-31

Family

ID=25230196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP45035324A Pending JPS4932604B1 (ja) 1969-04-29 1970-04-24

Country Status (5)

Country Link
US (1) US3587043A (ja)
JP (1) JPS4932604B1 (ja)
DE (1) DE2021081A1 (ja)
FR (1) FR2041217B1 (ja)
GB (1) GB1300165A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5151912A (ja) * 1974-11-01 1976-05-07 Teac Corp Teepurekooda
JPS5335502U (ja) * 1976-09-01 1978-03-29

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761891A (en) * 1971-03-18 1973-09-25 Siemens Ag Circuit arrangement for synchronizing transmitters and receivers in data transmission systems
US3733585A (en) * 1971-06-07 1973-05-15 Post Office Systems for detecting errors in a digital transmission channel
DE2339007C2 (de) * 1972-08-04 1985-09-05 Datatape Inc., Pasadena, Calif. Verfahren und Schaltungsanordnung zum Einfügen von Synchronisiersignalen
DE2339026C2 (de) * 1972-08-04 1983-10-27 Bell & Howell Co., 60645 Chicago, Ill. Verfahren und Schaltungsanordnung zum Entfernen von Paritätsbits aus Binärwörtern
US3804982A (en) * 1972-08-10 1974-04-16 Texas Instruments Inc Data communication system for serially transferring data between a first and a second location
GB1395856A (en) * 1972-12-04 1975-05-29 Siemens Ag Teleprinter systems
US3963869A (en) * 1974-12-02 1976-06-15 Bell Telephone Laboratories, Incorporated Parity framing of pulse systems
US4425645A (en) 1981-10-15 1984-01-10 Sri International Digital data transmission with parity bit word lock-on
JPS5864844A (ja) * 1981-10-15 1983-04-18 Victor Co Of Japan Ltd 同期検出方式
US4412329A (en) * 1981-10-15 1983-10-25 Sri International Parity bit lock-on method and apparatus
DE3229696A1 (de) * 1982-08-10 1984-02-16 ANT Nachrichtentechnik GmbH, 7150 Backnang Verfahren zur synchronuebertragung rahmenstrukturierter daten
DE3229695A1 (de) * 1982-08-10 1984-02-16 ANT Nachrichtentechnik GmbH, 7150 Backnang Verfahren zur synchronuebertragung von seriellen, wortweise geordneten digitalen daten
US4680765A (en) * 1985-07-26 1987-07-14 Doland George D Autosync circuit for error correcting block decoders
DE3718632C1 (de) * 1987-06-03 1988-08-25 Deutsche Forsch Luft Raumfahrt Verfahren zur Dekodierung von Daten
US5228041A (en) * 1987-06-12 1993-07-13 Matsushita Electric Industrial Co., Ltd. Sync signal detection system in a memory system for recording and reproducing block unit data
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US6150855A (en) * 1990-02-06 2000-11-21 Bull, S.A. Phase-locked loop and resulting frequency multiplier
FR2664770A1 (fr) * 1990-07-11 1992-01-17 Bull Sa Procede et systeme de transmission numerique de donnees en serie.
FR2664765B1 (fr) * 1990-07-11 2003-05-16 Bull Sa Dispositif de serialisation et de deserialisation de donnees et systeme de transmission numerique de donnees en serie en resultant.
FR2664769A1 (fr) * 1990-07-11 1992-01-17 Bull Sa Dispositif d'echantillonnage de donnees et systeme de transmission numerique de donnees en resultant.
US5485476A (en) * 1993-06-14 1996-01-16 International Business Machines Corporation Method and system for error tolerant synchronization character detection in a data storage system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3159811A (en) * 1961-06-29 1964-12-01 Bell Telephone Labor Inc Parity synchronization of pulse code systems
US3188569A (en) * 1962-12-14 1965-06-08 Bell Telephone Labor Inc Receiver input unit-synchronizing circuit
BE656364A (ja) * 1963-11-29

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5151912A (ja) * 1974-11-01 1976-05-07 Teac Corp Teepurekooda
JPS5335502U (ja) * 1976-09-01 1978-03-29

Also Published As

Publication number Publication date
FR2041217A1 (ja) 1971-01-29
DE2021081A1 (de) 1970-11-12
US3587043A (en) 1971-06-22
GB1300165A (en) 1972-12-20
FR2041217B1 (ja) 1975-07-04

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