JPS4876059A - - Google Patents

Info

Publication number
JPS4876059A
JPS4876059A JP584972A JP584972A JPS4876059A JP S4876059 A JPS4876059 A JP S4876059A JP 584972 A JP584972 A JP 584972A JP 584972 A JP584972 A JP 584972A JP S4876059 A JPS4876059 A JP S4876059A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP584972A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP584972A priority Critical patent/JPS4876059A/ja
Priority to FR7300848A priority patent/FR2167939B1/fr
Priority to DE19732301277 priority patent/DE2301277A1/de
Priority to NL7300548A priority patent/NL7300548A/xx
Publication of JPS4876059A publication Critical patent/JPS4876059A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H05K3/4667—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP584972A 1972-01-14 1972-01-14 Pending JPS4876059A (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP584972A JPS4876059A (it) 1972-01-14 1972-01-14
FR7300848A FR2167939B1 (it) 1972-01-14 1973-01-11
DE19732301277 DE2301277A1 (de) 1972-01-14 1973-01-11 Verfahren zum herstellen mehrschichtiger verbindungskonstruktionen, z.b. fuer integrierte halbleiterschaltkreise
NL7300548A NL7300548A (it) 1972-01-14 1973-01-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP584972A JPS4876059A (it) 1972-01-14 1972-01-14

Publications (1)

Publication Number Publication Date
JPS4876059A true JPS4876059A (it) 1973-10-13

Family

ID=11622437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP584972A Pending JPS4876059A (it) 1972-01-14 1972-01-14

Country Status (4)

Country Link
JP (1) JPS4876059A (it)
DE (1) DE2301277A1 (it)
FR (1) FR2167939B1 (it)
NL (1) NL7300548A (it)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5610998A (en) * 1979-07-09 1981-02-03 Hitachi Ltd Method of manufacturing ceramic multilayer wiring substrate

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2611871A1 (de) * 1975-03-26 1976-10-07 Honeywell Inf Systems Elektrische schaltungsbaugruppe in mehrschichtbauweise und verfahren zu deren herstellung
US4302625A (en) * 1980-06-30 1981-11-24 International Business Machines Corp. Multi-layer ceramic substrate
FR2490059A1 (fr) * 1980-09-09 1982-03-12 Serras Paulet Edouard Circuit imprime et son procede de fabrication
US4645552A (en) * 1984-11-19 1987-02-24 Hughes Aircraft Company Process for fabricating dimensionally stable interconnect boards
JPS6276600A (ja) * 1985-09-29 1987-04-08 株式会社　アサヒ化学研究所 基板に導電回路を形成する方法
GB8909729D0 (en) * 1989-04-27 1990-04-25 Ici Plc Compositions
JP4731976B2 (ja) * 2004-12-15 2011-07-27 株式会社トクヤマ メタライズドセラミック基板の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5610998A (en) * 1979-07-09 1981-02-03 Hitachi Ltd Method of manufacturing ceramic multilayer wiring substrate

Also Published As

Publication number Publication date
FR2167939A1 (it) 1973-08-24
DE2301277A1 (de) 1973-08-02
FR2167939B1 (it) 1975-03-28
NL7300548A (it) 1973-07-17

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