JPH1197628A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can be saved, even if its input threshold goes out so standard due to manufacturing process fluctuations or the like. SOLUTION: Input circuits 21 to 29 of a semiconductor device 1000 are constructed for voltage comparison circuits, respectively, and their reference voltage is applied from an internal voltage generating circuit 33, whose input voltage can be changed by a setting supplied from an external source. By changing the setting of the circuit 33 of the semiconductor device having a defective threshold, such a defect of the semiconductor device can be turned into a nondefective recovered. Furthermore, preferably the size of the chip can be reduced by collectively arranging the fuse elements of the circuit 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device that performs a predetermined process in response to an external input signal.

[0002]

2. Description of the Related Art At the stage of manufacturing a semiconductor device, the threshold value of an input circuit often fluctuates due to fluctuations and variations in the manufacturing process. When the fluctuation of the threshold value of such an input circuit is large, the "H"
The pulse widths of the logic and the “L” logic are changed.

For example, in a semiconductor memory device that responds at high speed, if the write / read pulse width changes due to the above-mentioned threshold variation, the margin of the circuit operation becomes insufficient, and the write / read operation is not performed normally. There is.

[0004] In such a case, the semiconductor device is defective due to a threshold failure of the input circuit. In many cases, the input circuit has a threshold adjustment function. However, since the adjustment is performed by changing the metal wiring mask pattern during the manufacturing process, such a defective product cannot be repaired.

FIG. 10 is a diagram showing a configuration of a conventional semiconductor device. The problem of the input circuit will be described in more detail with reference to FIG.

In FIG. 10, a semiconductor device 5000 includes:
Input terminals 451 to 459 for receiving external signals, input circuits 461 to 469 for receiving external signals received by the input terminals 451 to 459, and input circuits 461 to 461, respectively.
Internal circuit 4 which receives output signal of H.469 and performs predetermined processing
71.

FIG. 11 shows the input circuit 461 shown in FIG.
FIG. 3 is a circuit diagram showing an example of the configuration of FIG. The input circuit 463
To 469 have the same configuration as the input circuit 461.

Referring to FIG. 11, input circuit 461 includes transistors 501-513 and switches 515-517.
, Nodes N51, N52, N53, and inverter 51
9 is included.

Transistors 501 and 503 are connected in series between power supply node VCC and node N52 for outputting internal signal VOUT. The gate of transistor 501 is connected to node N51 receiving input signal VIN. Connected to node N53 receiving interlock signal φ.

Transistors 505 and 507 are connected in parallel between ground node GND and node N52 for outputting internal signal VOUT. The gate of transistor 505 is connected to node 51 receiving input signal VIN. Connected to node N53 receiving interlock signal φ.

Transistors 509 and 511 and switch 515 are connected in series between power supply node VCC and node N52, and the gate of transistor 509 is connected to node N5.
1 and the gate of the transistor 511 is connected to the node N5
3 is connected.

The transistor 513 and the switch 517 are connected in series between the ground potential GND and the node N52,
The gate of the transistor 513 is connected to the node N53.

The inverter 519 includes transistors 501 to
513, the internal signal VOUT output to the node N52 is inverted, and the output signal OUT of the input circuit 461 is output.

FIG. 12 is an input / output characteristic diagram for explaining the operation of the input circuit 461 of FIG. Referring to FIG. 12, waveform 531 shows a characteristic of internal signal VOUT with respect to input signal VIN when switches 515 and 517 are in an open state.

At the time when input circuit 5100 receives input signal VIN, normal interlock signal φ is "L".
Level.

Since the switches 515 and 517 are open, the transistors 509 to 513 are connected to the internal signal VOU.
It does not affect T. Interlock signal φ is "L"
Therefore, the transistor 503 is turned on and the transistor 507 is turned off.

When the voltage level of input signal VIN is 0 to V1, transistor 505 is off, and transistor 501 is on.

Therefore, internal signal VOUT attains an "H" state as shown in FIG. On the other hand, when the voltage level of the input signal VIN is V2 or more, the transistor 505
Is on, and the transistor 501 is off.
Therefore, the internal signal VOUT is in the “L” state as shown in FIG.

When the voltage level of the input signal VIN is V1
If it is between V2 and V2, the current flowing through transistors 501 and 505 is determined according to the voltage level of input signal VIN, and the level of internal signal VOUT is determined.

Here, when the switch 515 is turned on, the transistor 511 is in a conductive state, and the transistor 509 is in a state where the current flowing changes according to the voltage level of the input signal VIN. Transistors 509, 51
The internal signal VOUT shifts to the “H” side due to the current component flowing through 1 when the switch 515 is in the open state, and exhibits the characteristic of the waveform 535 shown in FIG.

Conversely, the switch 515 is open,
When the switch 517 is turned on, the switch 515,
517, compared to when both are open.
The current flowing from the gate to the ground node increases, and the internal signal VOUT shifts to the “L” side, and the waveform 53 shown in FIG.
3 will be obtained.

As described above, in the input circuit 461, the input circuit VIN is inverted, and the internal signal VOUT is generated. The internal signal VOUT for the input signal VIN is
The input / output characteristics are changed by appropriately setting the conduction state of the switches 5 and 517. Therefore, the threshold of the input circuit 461 can be adjusted by the switches 515 and 517.

FIG. 13 shows the input circuit 46 described with reference to FIG.
Input circuit 5 as a second example used in place of configuration 1
FIG. 2 is a circuit diagram showing a configuration of the embodiment 200.

Referring to FIG. 13, input circuit 5200 includes:
Transistors 511 to 565 and nodes N61 and N6
2, N63, switches 567 and 569, and an inverter 571.

Transistor 551 is connected between power supply node VCC and node N61, and receives an interlock signal φ at its gate. Transistor 553 and transistor 559 are connected in series at node N63, which is a connection node between node N61 and ground node GND. Transistor 561 is connected between node N63 and ground node G.
ND, and receives an interlock signal at the gate. Switch 567 and transistor 557 are connected in series between node N63 and ground node GND.
The gates of transistors 557 and 557 both receive input signal VIN. Transistor 555 and transistor 5
63 is connected in series between node N61 and ground node GND. Hereinafter, a connection node between the transistor 555 and the transistor 563 is referred to as a node N62. Switch 569 and transistor 565 are connected in series between node N62 and ground node GND. Transistors 563 and 565 both receive reference voltage signal Vref1 at their gates. The gate of the transistor 555 and the gate of the transistor 553 are both connected to the node N62, and the transistors 555 and 553 form a current mirror circuit. Inverter 571 receives and inverts internal signal VOUT output to node N63 to invert input signal 5200.
Output signal OUT.

FIG. 14 is an input / output characteristic diagram for explaining the operation of input circuit 5200 in FIG. Referring to FIG.
A waveform 581 indicates a characteristic of the internal signal VOUT with respect to the input signal VIN when the switches 567 and 569 are in an open state.

At the time when input circuit 5200 receives input signal VIN, normal interlock signal φ is "L".
Level, the transistor 551 supplies current to the transistors 553 and 555, and the transistor 561
Is in a non-conductive state.

When the switches 567 and 569 are open, the transistors 557 and 565 are connected to the node N
63, N62 and transistors 553, 55
5, 559 and 563 constitute a comparison circuit which compares the reference voltage signal Vref1 with the input signal VIN and inverts and outputs the result.

Therefore, when VIN <Vref1,
VOUT is in the “H” state, and when VIN> Vref1, the internal output signal VOUT is in the “L” state.

Here, when the switch 567 is turned on, at the threshold value of the comparison circuit, the current flowing through the transistor 563 causes the transistors 557, 559
Is equal to the sum of the currents flowing through. Therefore, the threshold value of the comparison circuit falls below Vref1 to V3,
The input / output characteristics of input circuit 5200 shift as shown by waveform 583.

Conversely, when the switch 569 is turned on and the switch 567 is opened, the sum of the currents flowing through the transistors 563 and 565 becomes equal to the current flowing through the transistor 559 at the threshold value of the comparison circuit. Therefore, the threshold value of the comparison circuit is Vref1
V4 rises further, and the input / output characteristics of the input circuit 5200 shift as shown by the waveform 585.

[0032]

As described above, in the conventional semiconductor device 5000, the input circuit 461 shown in FIG. 11 and the input circuit 5200 shown in FIG. , "OFF", it was possible to adjust the threshold value for each input circuit. However, the adjustment is performed by switching the wiring connection by replacing the photomask. Therefore, it has not been possible to remedy a semiconductor device having a threshold failure due to variations and variations in the manufacturing process.

It is also conceivable that the switch is formed by a fuse element or the like and cut off when a threshold failure occurs.
The area occupied by the semiconductor device is large, and it is difficult to accommodate the semiconductor device in an input circuit and arrange it near an input terminal.

Although it is conceivable to separate and arrange only the fuse element, a long wiring is added to the transistor portion in the input circuit, which is not preferable for operating the input circuit at high speed. In particular, when a comparison circuit is used for the input portion, it is preferable that the transistors constituting the comparison circuit have uniform characteristics, and they need to be arranged close to each other. It is not possible to arrange a fuse element between the transistors. Was.

An object of the present invention is to adjust a threshold value of an input circuit in a semiconductor device which receives an input signal from the outside and performs predetermined processing when a threshold value of an input circuit fluctuates due to a fluctuation or variation in a manufacturing process. By doing so, it is possible to provide a semiconductor device that can operate normally.

[0036]

According to a first aspect of the present invention, there is provided a semiconductor device comprising a plurality of input terminals and a plurality of input processing means for respectively receiving input signals input to the plurality of input terminals. Performs an operation of detecting the level of the input signal according to a corresponding threshold value serving as a criterion, receives an output signal of the plurality of input processing means, performs an internal circuit for performing predetermined processing, a reference voltage generation means, Reference voltage generating means for receiving an output voltage value of the reference voltage generating means and outputting a voltage corresponding to a corresponding threshold value, wherein the reference voltage generating means is externally connected when checking operation of the semiconductor device. Output voltage setting means capable of changing the voltage corresponding to the corresponding threshold value in accordance with the setting of (1).

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the reference voltage generating means includes:
Provided corresponding to each of the plurality of input processing means,
The internal voltage generator further includes a plurality of internal voltage generators, and each internal voltage generator outputs a corresponding threshold value to a corresponding input processing unit based on an output voltage value of the reference voltage generator.

According to a third aspect of the present invention, in addition to the configuration of the semiconductor device of the first aspect, the reference voltage generating means further comprises:
An internal voltage generating means for receiving an output voltage value of the reference voltage generating circuit and outputting a corresponding threshold commonly used by a plurality of input processing means is further included.

According to a fourth aspect of the present invention, in addition to the configuration of the semiconductor device of the first aspect, the plurality of input processing means includes a first plurality of groups of first input processing means and a second plurality of input processing means. Reference voltage generating means receiving the output voltage value of the reference voltage generating means, and a corresponding threshold value commonly used in the first input processing means group. And a second internal voltage for receiving the output voltage value of the reference voltage generation circuit and outputting a corresponding threshold value commonly used in the group of the second input processing means. Generating means.

According to a fifth aspect of the present invention, in addition to the configuration of the semiconductor device according to the fourth aspect, the semiconductor device is formed on a main surface of a semiconductor substrate, and the first internal voltage generating means includes a fuse element. The first internal voltage generating means includes a second setting means for setting a corresponding threshold value by the on / off of the fuse element. The first setting means and the second setting means are respectively disposed in first and second regions obtained by dividing a predetermined region on the main surface of the semiconductor substrate.

According to a sixth aspect of the present invention, there is provided the semiconductor device according to the second aspect.
In addition to the configuration of the semiconductor device described in 3, 4, or 5, the reference voltage generating means includes a first node to which a first potential is supplied, a second node to which a second potential is supplied, A constant current means and a resistance means connected in series between the first node and the second node, and a corresponding threshold value is supplied from a connection node between the constant current means and the resistance means; , A first constant current circuit that supplies current to the connection node, a fuse element connected in series between the first node and the connection node, and a second constant current circuit.

According to a seventh aspect of the present invention, there is provided a semiconductor device according to the second aspect.
6. The semiconductor device according to 3, 4, or 5. In addition to the above configuration, the reference voltage generating means includes a first node to which a first potential is supplied, a second node to which a second potential is supplied, a first node and a second node. A constant current means and a resistance means connected in series between the constant current means and the resistance means to supply a corresponding threshold value from a connection node between the constant current means and the resistance means. A first resistance element connected therebetween, a fuse element and a second resistance element connected in series between the second node and the connection node;

The semiconductor device according to the eighth aspect is the second aspect.
In addition to the configuration of the semiconductor device described in 3, 4, or 5, the reference voltage generating means includes a first node to which a first potential is supplied, a second node to which a second potential is supplied, A constant current means and a resistance means connected in series between the first node and the second node, and a corresponding threshold value is supplied from a connection node between the constant current means and the resistance means; A first resistance element connected between the connection node and the third node; a fuse element and a second resistance element connected in parallel between the third node and the second node; .

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a semiconductor device 1000 according to a first embodiment of the present invention.

In FIG. 1, a semiconductor device 1000 has input terminals 1 to 9 for receiving signals from the outside and input terminals 1 to 9.
Input circuit 1 for receiving each of the external signals received by 9
1 to 19 are provided.

Each of input circuits 11 to 19 performs an operation of detecting the level of an external signal according to a corresponding threshold value serving as a criterion.

The semiconductor device 1000 includes input circuits 11 to 1
9, an internal circuit 32 for performing predetermined processing such as data storage processing, etc., and a reference voltage generating circuit 31.
And a reference voltage generation circuit 33 that receives an output voltage value of the reference voltage generation circuit 31 and outputs a threshold value corresponding to each of the input circuits 11 to 19.

The reference voltage generation circuit 33 outputs a threshold value corresponding to each of the input circuits 11 to 19 based on the output voltage value of the reference voltage generation circuit 31.
1 to 29.

FIG. 2 is a circuit diagram showing an example of the configuration of input circuit 11 shown in FIG. The input circuits 13 to 19 shown in FIG. 1 have the same configuration as the input circuit 11.

Referring to FIG. 2, input circuit 11 includes transistors 51 to 56, nodes N1, N2, N3, and an inverter 57.

Transistor 51 is connected between power supply node VCC and node N1, and receives an interlock signal φ at its gate. Transistor 52 and transistor 54 are connected in series at node N63, which is a connection node between node N1 and ground node GND. Transistor 55 is connected between node N2 and ground node GND, and receives an interlock signal φ at its gate.

Transistor 55 and transistor 56 are connected in series at node N3 which is a connection node between node N1 and ground node GND.

The gates of transistors 52 and 53 are both connected to node N3, and transistors 52 and 53 constitute a current mirror circuit. The gate of the transistor 54 receives the input signal VIN from the outside, and the transistor 5
The gate of No. 6 receives the reference voltage Vref3.

When interlock signal φ is in the "L" state, transistor 51 supplies current to transistors 52 and 53, and transistor 55 is off.

In this case, the transistors 52, 53, 5
Reference numerals 4 and 56 constitute a comparison circuit that compares the reference voltage signal Vref3 with the input signal VIN and inverts the result to the inverter 57.

Therefore, the semiconductor device 1 of the first embodiment
000, the threshold values of the input circuits 11, 13, 15, 17, 19 are equal to the internal voltage generation circuits 21, 23, 25, 2,
7, 29 are input circuits 11, 13, 15, 1
Reference voltage values to be output to 7 and 19.

FIG. 3 shows the reference voltage generating circuit 3 shown in FIG.
1 is a circuit diagram illustrating an example of a configuration of FIG.

Referring to FIG. 3, reference voltage generating circuit 31
Includes transistors 101 to 107 and a resistor 109.

Transistor 101 and transistor 105
Is connected between power supply node VCC and ground node GND at node N21 which is a connection node. Transistor 103 and transistor 107 are connected at node N22, which is a connection node between power supply node VCC and node N23. The gates of the transistors 101 and 103 are both connected to the node N22.
Reference numerals 1 and 103 constitute a current mirror circuit. Resistance 10
9 is connected between node N23 and ground node GND. The node N23 is connected to the gate of the transistor 105, and the node N21 is connected to the gate of the transistor 107.
Is connected.

With the above configuration, the voltage of the node N22 becomes constant and the reference voltage Vref2 is generated.

FIG. 4 shows the internal voltage generating circuit 2 shown in FIG.
FIG. 2 is a circuit diagram showing a first example of the configuration of FIG. The internal voltage generating circuits 23 to 29 shown in FIG.
1 has the same configuration as that of FIG.

Referring to FIG. 4, internal voltage generating circuit 21 includes a transistor 151, resistors 153 to 157, and fuse elements 159 and 161. Resistance 153, 155, 1
57 is connected in series between node N31 and ground node GND. Fuse elements 159 and 161 are resistors 15
5 and 157, respectively.

The transistor 151 has a gate connected to the reference voltage V.
Upon receiving ref2, a constant current is supplied from the power supply node VCC to the node N31.

Therefore, reference voltage Vref3 output from internal voltage generating circuit 21 is determined by the resistance between node N31 and ground node GND. However, when fuse elements 159 and 161 are not blown, reference voltage Vref3 is not changed.
3 is a value determined by the resistance value of the resistor 153.

If the input threshold value of the semiconductor device 1000 is too low with respect to the standard value, the fuse element 1
By cutting 59 or fuse element 161, the resistance value between node N31 and ground node GND increases,
On the other hand, since the flowing current is a constant current supplied by the transistor 151, the reference voltage Vref serving as a threshold value
3 rises. In this manner, the threshold value is adjusted by cutting the fuse, and a non-standard semiconductor device can be determined as a non-defective product.

[First Modification of First Embodiment] Next, a first modification of the first embodiment will be described.

The semiconductor device of the first modification of the first embodiment differs from the semiconductor device of the first embodiment in that the internal configuration of internal voltage generating circuit 21 is different from the circuit shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of an internal voltage generating circuit 1400 used in place of internal voltage generating circuit 21 described in FIG.

Referring to FIG. 5, internal voltage generating circuit 140
0 includes a transistor 201, resistors 203 to 207, fuse elements 209 and 211, and a node N41. Resistance 203 is connected between node N41 and ground node GND. Fuse element 209 and resistor 205 connected in series are similarly connected between node N41 and ground node GND.

Fuse element 211 and resistor 207 connected in series are similarly connected between node N41 and ground node GND.

Transistor 201 receives reference voltage Vref2 at its gate, and supplies a constant current from power supply node VCC to node N41.

Therefore, reference voltage Vref3 output from internal voltage generating circuit 1400 is determined by the resistance value between node N41 and ground node GND. However, when fuse elements 209 and 211 are not cut, reference voltage Vr3 is output.
ef3 is a value determined by the combined resistance of the resistors 203, 205, and 207.

If the input threshold value of the semiconductor device 1000 is too high with respect to the standard value, the fuse element 2
09 or by cutting the fuse element 211, the resistance value between the node N41 and the ground node GND decreases,
On the other hand, since the flowing current is a constant current supplied by the transistor 201, the reference voltage Vre serving as the threshold
f3 rises. By cutting the fuse in this way, the threshold value can be adjusted, and a non-standard semiconductor device can be made a non-defective product.

[Modification 2 of Embodiment 1] Next, Modification 2 of Embodiment 1 will be described.

The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first embodiment in that the internal configuration of internal voltage generating circuit 21 is different from the circuit shown in FIG.

FIG. 6 is a circuit diagram showing a configuration of an internal voltage generation circuit 1500 used in place of internal voltage generation circuit 21 described in FIG.

Referring to FIG. 6, internal voltage generating circuit 150
0 indicates transistors 251 to 255, a resistor 257,
Fuse elements 259 and 261 are included.

The resistor 257 is connected between the node N45 and the ground node G.
ND. Transistor 251 is connected to power supply node VCC and node N45, and transistor 2
53 and 255 are connected in parallel to the transistor 251 via fuse elements 259 and 261 respectively.

The gates of transistors 251, 253 and 255 receive reference voltage Vref2 and supply a constant current to node N45.

Therefore, reference voltage Vref3 output from internal voltage generation circuit 1500 is
It is determined by the sum of the current values supplied to the resistor 257 by 253 and 255.

If the input threshold of the semiconductor device 1000 is too high with respect to the standard value, the fuse element 2
If the amount of current supplied to the node N51 is reduced by cutting the fuse 59 or the fuse element 261, the threshold value Vref3 decreases.

By cutting the fuse in this way, the threshold value can be adjusted and a non-standard semiconductor device can be obtained as a non-defective product.

[Second Embodiment] FIG. 7 is a block diagram showing a configuration of a second embodiment of the present invention.

In the semiconductor device 2000 of the second embodiment, the reference voltage generation circuit 33 of the configuration of the semiconductor device 1000 of the first embodiment becomes the internal voltage generation circuit 321 and the input circuit 1
The semiconductor device 1000 differs from the semiconductor device 1000 of the first embodiment in that a common reference voltage is supplied to 1 to 19.

Since other structures are the same as those of semiconductor device 1000 described in the first embodiment, the same portions in FIG. 7 are denoted by the same reference characters, and description thereof will not be repeated.

In FIG. 7, internal voltage generating circuit 321 of semiconductor device 2000 has the same configuration as internal voltage generating circuit 21 described in the first embodiment.

The internal voltage generation circuit 321 of the semiconductor device 2000 is different from the internal voltage generation circuit 1400 described in the first modification of the first embodiment or the internal voltage generation circuit 1500 described in the second modification of the first embodiment. The same configuration may be used.

In the semiconductor device 2000 of the second embodiment,
The reason for adjusting the thresholds of the input circuits 11 to 19 is that
Only the internal voltage generation circuit 321 is provided.

Therefore, if the fuse element included in internal voltage generating circuit 321 is cut, input circuits 11-19
All thresholds can be adjusted simultaneously. Therefore, the adjustment time can be reduced, and the number of internal voltage generating circuits including fuse elements occupying a large area on the semiconductor substrate is reduced, which is advantageous in reducing the chip size of the semiconductor device.

[Third Embodiment] FIG. 8 is a block diagram showing a configuration of a semiconductor device 3000 according to a third embodiment of the present invention.

In the semiconductor device 3000 of the third embodiment, the reference voltage generation circuit 33 of the semiconductor device 1000 of the first embodiment is constituted by the internal voltage generation circuits 371 and 373, and the internal voltage generation circuit 371 is connected to the input circuit 11 15 is different from the semiconductor device 1000 of the first embodiment in that the internal voltage generating circuit 373 supplies a common reference voltage to the input circuits 17 and 19.

Since the other structure is the same as semiconductor device 1000 described in the first embodiment, the same portions in FIG. 8 are denoted by the same reference characters, and description thereof will not be repeated.

In FIG. 8, internal voltage generating circuits 371 and 373 of semiconductor device 3000 have the same configuration as internal voltage generating circuit 21 described in the first embodiment.

The internal voltage generating circuits 371 and 373 of the semiconductor device 3000 are the same as the internal voltage generating circuit 1400 described in the first modification of the first embodiment or the internal voltage generating circuit described in the second modification of the first embodiment. The configuration may be the same as 1500.

In the semiconductor device 3000 of the third embodiment,
The reason for adjusting the thresholds of the input circuits 11 to 19 is that
There are two internal voltage generation circuits 371 and 373.

Therefore, by cutting the fuse element included in internal voltage generating circuit 371, input circuits 11-15
Can be adjusted at the same time, and by cutting a fuse included in internal voltage generation circuit 373, input circuit 1 can be adjusted.
The thresholds 7 and 19 can be adjusted simultaneously.

Some semiconductor devices have, for example, both a terminal group having a TTL input threshold and a terminal group having a CMOS input threshold, and such a semiconductor device can be dealt with. Becomes

Further, the adjustment time can be shortened, and the number of internal voltage generating circuits including fuse elements occupying a large area on the semiconductor substrate is reduced, which is advantageous in that the chip size of the semiconductor device is reduced.

[Fourth Embodiment] FIG. 9 is a block diagram showing a configuration of a fourth embodiment of the present invention.

In the semiconductor device 4000 of the fourth embodiment, the internal voltage generating circuits 371 and 373 of the configuration of the semiconductor device 3000 of the third embodiment are arranged close to each other, and the fuse elements included in the internal voltage generating circuits 371 and 373 are A predetermined region on the main surface of the semiconductor substrate is arranged in each of the divided regions.

Although the fuse element occupies a large area on the semiconductor substrate, it is necessary to surround the fuse element with a guard ring so as not to damage peripheral circuits when the fuse is cut. In the case where the number of fuse elements is large, it is disadvantageous in terms of the area occupied on the semiconductor substrate if each fuse element is surrounded by a guard ring one by one.

Therefore, the semiconductor device 4 of the fourth embodiment
000, fuse elements are collectively arranged in one area,
The periphery can be surrounded by a common guard ring, which is advantageous in terms of the area occupied on the semiconductor substrate.

[0103]

According to the semiconductor device of the first aspect, it is possible to adjust the threshold value of the input circuit when confirming the operation. Therefore, even if the threshold value of the input circuit is out of the specified range due to a variation or variation in the manufacturing process, the threshold value of the input circuit is adjusted for each semiconductor device to be within the specified range. Therefore, a semiconductor device that has once become a nonstandard product can be remedied and a nondefective product can be obtained.

In the semiconductor device according to the second aspect, it is possible to adjust the threshold value of the input circuit when confirming the operation. Therefore, even if the threshold value of the input circuit is out of the specified range due to a variation or variation in the manufacturing process, the threshold value of the input circuit is adjusted for each semiconductor device to be within the specified range. Therefore, a semiconductor device that has once become a nonstandard product can be remedied and a nondefective product can be obtained.

According to the semiconductor device of the third aspect, in addition to the effect of the semiconductor device of the first aspect, the threshold value of each input circuit is supplied at a common node, and the threshold voltage is determined by one internal voltage generation circuit. Since the value adjustment is performed, the adjustment time can be reduced, and the number of the internal voltage generating circuits occupying a large area on the semiconductor substrate is one, which is advantageous in that the chip size of the semiconductor device is reduced.

According to the semiconductor device of the fourth aspect, in addition to the effect of the semiconductor device of the first aspect, a threshold value is supplied at a common node for each group including a plurality of input circuits, and Since the threshold adjustment is performed by one internal voltage generating circuit, it is possible to cope with a case where a plurality of input terminal groups having different input standard values are required. Further, the adjustment time can be reduced, and the number of internal voltage generating circuits occupying a large area on the semiconductor substrate is reduced, which is advantageous in that the chip size of the semiconductor device is reduced.

In the semiconductor device according to the fifth aspect, in addition to the effect of the semiconductor device according to the fourth aspect, setting parts including fuse elements of an internal voltage generating circuit occupying a large area on the semiconductor substrate are collectively arranged. Thus, the area of the guard ring portion can be reduced, which is more advantageous in terms of the area occupied by the semiconductor device.

The semiconductor device according to the sixth aspect is the second aspect.
In addition to the effects of the semiconductor device described in 3, 4 or 5, the threshold voltage can be adjusted by selectively cutting the fuse element. In this case, threshold adjustment can be facilitated.

The semiconductor device according to claim 7 has the following features.
In addition to the effects of the semiconductor device described in 3, 4, or 5, the threshold voltage can be adjusted by selectively cutting the fuse element. In this case, threshold adjustment can be facilitated.

The semiconductor device according to the eighth aspect is the second aspect.
In addition to the effects of the semiconductor device described in 3, 4 or 5, the threshold voltage can be adjusted by selectively cutting the fuse element. In this case, threshold adjustment can be facilitated.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device 1000 according to a first embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 2 is a circuit diagram showing details of an input circuit 11 of FIG. 1;

FIG. 3 is a circuit diagram showing details of a reference voltage generation circuit 31 of FIG. 1;

FIG. 4 is a circuit diagram showing details of an internal voltage generation circuit 21 of FIG. 1;

FIG. 5 is a circuit diagram showing details of an internal voltage generation circuit 1400 showing a first modification of the internal voltage generation circuit 21 of FIG. 1;

FIG. 6 is a circuit diagram showing details of an internal voltage generation circuit 1500 showing a second modification of the internal voltage generation circuit 21 of FIG. 1;

FIG. 7 shows a semiconductor device 2000 according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 8 shows a semiconductor device 3000 according to a third embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 9 shows a semiconductor device 4000 according to a fourth embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 10 is a block diagram showing a configuration of a conventional semiconductor device 5000.

11 is a circuit diagram showing a first example of details of an input circuit 461 in FIG. 10;

12 is an input / output characteristic diagram illustrating an operation of the input circuit 461 in FIG.

13 is a circuit diagram showing an input circuit 5200 which is a second example of the details of the input circuit 461 in FIG.

14 is an input / output characteristic diagram illustrating an operation of the input circuit 5200 in FIG.

[Explanation of symbols]

1 to 9, 451 to 459 input terminals, 11 to 19, 46
1 to 469, 5200 input circuits, 21 to 29, 140
0, 1500, 321, 371, 373 Internal voltage generation circuit, 33 reference voltage generation circuit, 31 reference voltage generation circuit, 51 to 56, 101 to 107, 151, 201, 2
51,501-513,551-565 transistors,
57, 519, 571 inverters, N1, N2, N
3, N21, N22, N23, N31, N32, N3
3, N41, N45, N51, N52, N53, N6
1, N62, N63 nodes, 109, 155, 15
7, 203, 205, 207, 257 resistance, 159,
161, 209, 211, 259, 261 fuse element, 515, 517, 567, 569 switch, 53
1-535, 581-585 waveforms.

Claims (8)

[Claims] 1. A semiconductor device for performing a predetermined process in response to an external input signal, comprising: a plurality of input terminals; and a plurality of input processing means for receiving the input signals input to the plurality of input terminals, respectively. Wherein each of the input processing means performs a detection operation on the level of the input signal in accordance with a corresponding threshold value serving as a criterion, receives output signals of the plurality of input processing means, and performs predetermined processing. Further comprising: an internal circuit for performing; a reference voltage generating means; and a reference voltage generating means for receiving an output voltage value of the reference voltage generating means and outputting a voltage corresponding to the corresponding threshold value, Means for setting output voltage setting means capable of changing a voltage corresponding to the corresponding threshold value in accordance with an external setting when confirming an operation of the semiconductor device; . 2. The reference voltage generating means further includes a plurality of internal voltage generating means provided corresponding to each of the plurality of input processing means, wherein each of the internal voltage generating means comprises: 2. The semiconductor device according to claim 1, wherein a value is output to a corresponding said input processing means based on an output voltage value of said reference voltage generation means. 3. An internal voltage generating means for receiving an output voltage value of the reference voltage generating circuit and outputting the corresponding threshold value commonly used by the plurality of input processing means. Claim 1 further comprising:
13. The semiconductor device according to claim 1. 4. The reference voltage generating means, wherein the plurality of input processing means includes a first plurality of groups of first input processing means and a second plurality of groups of second input processing means. A first internal voltage generating means for receiving the output voltage value of the reference voltage generating means and outputting the corresponding threshold value, which is used in common by the group of the first input processing means;
And a second internal voltage generation means for receiving the output voltage value of the reference voltage generation circuit and outputting the corresponding threshold value commonly used in the second input processing means group. 13. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein said semiconductor device is formed on a main surface of a semiconductor substrate, and said first internal voltage generating means includes first setting means for setting said corresponding threshold value by intermittently connecting a fuse element. Wherein the second internal voltage generating means includes a second setting means for setting the corresponding threshold value by switching a fuse element on and off, wherein the first setting means and the second setting means comprise: The semiconductor device according to claim 4, wherein a predetermined region on the main surface of the semiconductor substrate is arranged in each of the divided first and second regions. 6. The reference voltage generating means includes: a first node to which a first potential is supplied; a second node to which a second potential is supplied; the first node and the second node; A constant current means and a resistance means connected in series between the node and a node; and supplying the corresponding threshold value from a connection node between the constant current means and the resistance means; 4. A first constant current circuit for supplying a current to a node, a fuse element connected in series between the first node and the connection node, and a second constant current circuit. , 4 or 5. 7. The reference voltage generation means includes: a first node to which a first potential is supplied; a second node to which a second potential is supplied; A constant current unit and a resistance unit connected in series between the node and a node; and supplying the corresponding threshold value from a connection node between the constant current unit and the resistance unit; A first resistance element connected between the second node and the connection node, and a fuse element and a second resistance element connected in series between the second node and the connection node. The semiconductor device according to claim 2, 3, 4, or 5. 8. The reference voltage generating means includes: a first node to which a first potential is supplied; a second node to which a second potential is supplied; A constant current unit and a resistance unit connected in series between the node and a node; supplying the corresponding threshold value from a connection node between the constant current unit and the resistance unit; A first connected between a node and a third node
6. The semiconductor device according to claim 2, further comprising: a resistance element, and a fuse element and a second resistance element connected in parallel between the third node and the second node. 7. .