JP3263231B2 - Semiconductor device and burn-in method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ECL (Emitter Coup
The present invention relates to a semiconductor device such as a led Logic circuit and a burn-in method thereof. Here, burn-in refers to operating a circuit before actual operation in order to stabilize circuit characteristics and detect an initial failure of the circuit.

[0002]

2. Description of the Related Art First, a general circuit configuration and operation of an ECL circuit which is a circuit example to which a conventional burn-in method and a burn-in method of the present invention are applied will be described.

FIG. 16 shows an example of an ECL circuit. This E
The CL circuit is an OR / NOR gate of three inputs A, B, and C. When any one of the three inputs A, B, and C becomes higher than a reference potential _{Vref1 serving} as a circuit threshold, the transistor Q7 _a , Q7 _b . Only the transistor corresponding to the higher input of Q7 _c turns on, the other transistors and transistor Q6 turn off, and the current I
_cs flows through the current path corresponding to the turned-on transistor among the current paths P1, P2, and P3. Then, the node NZ
Potential becomes higher than Nodoba NZ, the output Z of the ECL circuit by the emitter follower output stage composed of an emitter follower output stage and transistors Q5 _b and a resistor R _a2 comprising transistors Q5 _a and the resistance R _a2 is to "H" (a high-) The level and output bar Z become "L" (low) level.

On the other hand, three input A, B, if all of the C is lower than the reference potential V _ref1, the transistors Q7 _a, Q
7 _b, Q7 _c is turned off and the transistor Q6 is turned on, a current I _cs of the constant current source 60 flows to the right of the current path P4.
Then, the potential of the node NZ becomes lower than the potential of the node NZ, and the output Z of the ECL circuit becomes "L" level and the output bar Z becomes "H" level by the emitter follower output stage. In this manner, the logical sum (= A + B + C) of the inputs A, B, and C is output from the output Z of the ECL circuit, and the negative logical sum (= bar (A + B + C)) is output from the output bar Z. In the ECL circuit, the reference potential V
_ref1 is generally the input signal A as shown in FIG. 17, B, C of "H" level (V _IH1, for example -0.8 V) to "L" level (V _{IL 1} for example -1.4 V) an intermediate level ( V _IM1
= (V _IH1 + V _IL1 ) / 2, for example, -1.1 V).

FIG. 18 shows another example of an ECL circuit.
This ECL circuit inputs the input A to the output Z by the selection signal S.
Alternatively, it is a two-input multiplexer that passes one of the inputs B. This ECL circuit has two reference potentials V _ref1 and V _ref
ref2 is required, and these reference potentials V _ref1 and V _ref2 and the “H” level (V _IH1 ,
Relationship between V _{the IH 2)} to the "L" level (V _IL1, V _IL2) is as shown in FIG. 19. That is, the reference potential V _ref1 is at an intermediate level V _IH1 and V _IL1, reference potential V _{re f2}
Is at an intermediate level between V _IH2 and V _IL2 . Where V _IH2 =
V _IH1 −φ, V _IL2 = V _IL1 −φ, where φ is the V _BE of the bipolar transistor and is generally 0.8V.

Examining the change over time of the failure rate of such an ECL circuit generally results in a bathtub curve as shown in FIG. This bathtub curve is divided into three periods, an initial failure period, a random failure period, and a wear failure period, according to the passage of time from its characteristics. In the initial failure period, a failure due to a design error, a defect in a process, or the like, which is latent in a circuit, becomes apparent as the use is started. In the accidental failure period, the failures of the component parts that did not appear in the initial failure period overlap and become apparent, but the failure rate is almost constant. In the wear failure period, the failure rate increases over time due to aging of the components.

[0007] In order to keep the product defect rate after shipment at or below a certain specified level, it is necessary for the manufacturer to select initial failure products and stabilize the failure rate at a low level. This process is called burn-in.
Normally, in the case of an integrated circuit, in the case of an integrated circuit, a non-defective chip whose function has been selected is sealed in a package, and a test pattern that can realize the actual circuit operation as comprehensively as possible is input and the circuit operation is performed. Make the connected failure factors obvious. For example, the EC shown in FIGS.
In the L circuit, each current path P1, P2, P3, P4
By switching an input signal (test pattern) so that a current flows through the path, a defect factor that is latent on each path is revealed.

[0008]

Here, a conventional burn-in method will be described with reference to FIG. ECL in FIG.
Each current path P1, P of the 3-input OR gate in the circuit
2. To burn-in by applying current to P3 and P4,
What is necessary is just to input four kinds of test patterns as shown in Table 1 to the input terminals A, B, and C.

[0009] Table 1 potential current path of the input terminal A B C H L L P1 L H L P2 L L H P3 L L L P4 However, all the circuit elements of a semiconductor integrated circuit in which a plurality of ECL circuits are connected to each other In order to carry out burn-in by passing a current through the device, an enormous test pattern must be input from many input terminals.

For example, in order to perform burn-in on the circuit shown in FIG. 21 in which two 3-input OR gates shown in FIG. 16 are connected in series, the input terminals A1 and B of the first OR gate OR1 are used.
1, C1 and input terminals B2 of the second OR gate OR2.
Six test patterns as shown in Table 2 must be input to C2.

Table 2 Potentials of input terminals Current paths A1, B1, C1, B2, C2 OR1 OR2 HLLLLL P1 P1 LHLLLP2 P1 LLLHLLP3 P1 LLLLLHLLP4 P2 LLLLHP4P3LLLLLP4P4 Note that the current paths P1 and P2 of the first and second OR gates in Table 2
P2, P3, and P4 also show the same paths as the current paths shown in FIG.

When a 3-bit coefficient circuit FF1, which is a sequential logic circuit, and inverters N1, N2, and N3 are inserted in a stage preceding the first OR gate 1 of the circuit shown in FIG. It gets complicated. The 3-bit coefficient circuit FF1 is a circuit composed of a flip-flop, and the output of the flip-flop changes every time the input signal is inverted, and counts how many times the flip-flop is inverted.

A signal waveform (test pattern) at each node of the circuit shown in FIG. 22 and a first waveform when these signals are given.
FIG. 23 shows a current path flowing through the OR gate 1 of FIG.

According to FIG. 23, for example, in order to flow a current through the current path P4, eight input pulses are not supplied to the input terminal of the 3-bit counting circuit FF1 after the reset terminal of the 3-bit counting circuit FF1 is set to "L". I understand that I can not do it.
Further, it can be seen that the current path P4 has less opportunity for current to flow than the other current paths P1, P2, and P3.

In today's semiconductor integrated circuits, there are those in which hundreds of thousands of gates are integrated on one chip and a complex sequential logic circuit using thousands of flips is formed. In order to perform burn-in on such a semiconductor integrated circuit, an enormous test pattern must be input from a large number of input terminals to operate for a long time.

In a semiconductor integrated circuit of today's general scale, the number of input terminals is hundreds, the test pattern required for performing burn-in is thousands to tens of thousands of steps, and the time required for burn-in of one chip is long. It can range from hours to tens of hours.

Since about 100 chips are lined up on one wafer, if it is assumed that these chips are burned in for 10 hours one by one, the time required for performing burn-in on one wafer is considered. Is 1000 hours (about 42 days), which is unrealistic.

Therefore, conventionally, each chip is sealed in a package and then mounted on a dedicated burn-in board, and burn-in is performed on many chips simultaneously.

In the conventional burn-in described above,
There are the following problems. 1) As described above, it takes time to perform burn-in on a single wafer. Therefore, each chip is sealed in a package before the test is performed. However, if the burn-in becomes defective after sealing in an expensive package. , Even that package is useless. This is a serious problem in the ECL circuit because an expensive package is often used in order to pursue high performance. 2) A burn-in board is required for each product or package type. 3) Test patterns must be input to many input terminals, which requires an expensive pulse generator. 4) In order to identify the cause of a defect by flowing a current through all the circuit elements included in the chip, an enormous test pattern is required, and it is necessary to perform the test for a longer time.

Such problems have recently become remarkable, such as diversification of chips (packages), increase of pins, shortened delivery time,
And so on.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor integrated circuit and a burn-in method for the same, which can reduce the time required for burn-in as much as possible.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor device burn-in method including a plurality of interconnected signal output circuits, each of which includes a differential circuit;
It is used in a semiconductor device that compares an input signal potential of the differential circuit with a reference potential and outputs an output signal in accordance with the comparison result. Setting the input signal of the signal output circuit to an intermediate level between the maximum level and the minimum level of the input signal,
The reference potential is set higher or lower than the input signal set to the intermediate level.

[0023]

Further, the semiconductor device according to the second aspect of the present invention includes a plurality of signal output circuits connected to each other, and each of the signal output circuits has a differential circuit. And a reference potential, and outputs an output signal in accordance with the comparison result. By short-circuiting between complementary output nodes of the differential circuit, the input signal potential of a subsequent signal output circuit is reduced. Setting means for setting an intermediate level between the maximum level and the minimum level; and setting the reference potential higher than the input signal potential set to the intermediate level during the normal operation and during the burn-in operation, Alternatively, there is provided a switching means for switching so as to be set low.

Further, in the above-mentioned semiconductor device, the switching means sets the reference potential higher than a maximum level of the input signal potential or lower than a minimum level of the input signal potential. And

[0026]

[0027]

[0028]

According to the burn-in method of the first aspect of the present invention, the reference potential is set to a level higher or lower than an intermediate level between the maximum level and the minimum level of the input signal of the semiconductor device. Therefore, this high or low level reference potential can be used as a burn-in test pattern.

[0029]

According to the semiconductor device of the second aspect of the present invention, the complementary output node of the differential circuit of the preceding signal output circuit is short-circuited between the plurality of interconnected signal output circuits. By setting the output signal, that is, the input signal potential of the subsequent signal output circuit to the intermediate level, and setting the reference potential to a level higher or lower than the intermediate level, the normal operation and the burn-in operation are performed. The level of the reference potential is made different from time to time. Thus, a plurality of current paths in a plurality of interconnected signal output circuits can be switched, and the time required for burn-in can be reduced.

Further, according to the above-described semiconductor device, the reference potential is set to a level higher or lower than the potential of the input signal of the semiconductor device. This also allows a plurality of current paths in the semiconductor device to be switched, and the time required for burn-in can be reduced.

[0032]

[0033]

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the burn-in method according to the first invention will be described with reference to FIGS. Burn method of this embodiment, the reference potential V _ref to be circuit threshold is one, used in the ECL circuit shown in FIG. 16, the reference potential V _ref1 to the burn-in, the input signal A,
By making the B and C higher than the “H” level V _IH1 or lowering the “L” level V _IL1,
The path of the current flowing through each gate of the CL circuit is simultaneously switched. For example, the “H” level V _ref1 (H) and the “L” level V _ref1 (L) of the reference potential V _ref1 are, as shown in FIG. 10, V _ref1 (H)> V _IH1 , V _ref1 (L) <V
Set to satisfy _IL1 . Note that during normal operation other than during burn-in, the reference potential V _ref1 is set to “H” level V _IH1 and “L” level V of the input signal as shown in FIG.
It is set to an intermediate level V _IM1 between _IL1.

[0035] If set to burn when the reference potential V _ref1 to the "H" level V _ref1 (H), 3 inputs signals A of the ECL circuit shown in FIG. 16, B, than the V _{re f1} any potential level of the C Since the current becomes lower, the current I _cs of the constant current source 60 flows through the path P4. Also, the reference potential V _{ref1 is set} to the “L” level
_When set to _ref1 (L), current flows only through the path of the transistor to which the input signal of the potential of the “H” level V _IH1 among the three input signals A, B, and C is input. For example, when the input signals A and B are V _IH1 and the input signal C is V _IL1 , current flows through two paths P1 and P2. At this time, in the ECL circuit of FIG.
Node potential of the NC V _IH1 -φ (φ usually in V _BE of the bipolar transistor, about 0.8 V) between the base and emitter of the transistor Q7 _c input C enters since the voltage V _BE
Is V _BE = V _IL1 − (V _IH1 −φ) = φ− (V _IH1 −
V _IL1 ) <φ, and the transistor Q7 _c is turned off. Therefore, no current flows through the path P3.

By setting the reference potential V _ref1 to the “H” level V _ref1 (H) or the “L” level V _ref1 (L), the current path of the ECL circuit shown in FIG. Can be switched as shown in FIG.

Table 3 V _ref1 potential Current path V _ref1 (L) One or more of P1, P2, P3 V _ref1 (H) P4 As described above, according to the present embodiment, the current path is switched only by setting the level of the reference potential V _ref1 to “H” level V _ref1 (H) or “L” level V _ref1 (L) at the time of burn-in. Thus, the time required for burn-in can be significantly reduced as compared with the conventional case (Table 1).

[0038] Further the burn method of the first embodiment is also applicable to an integrated circuit ECL circuit of Figure 16 is formed by a plurality of stages interconnected, the reference potential V _ref is all ECL
Since the current is commonly supplied to the circuits, the current paths of all the ECL circuits can be switched at the same time, and the time required for burn-in can be greatly reduced.

Next, a second embodiment of the burn-in method according to the first invention will be described with reference to FIGS.
The burn-in method of this embodiment is used for the ECL circuit shown in FIG. 18 in which there are two reference potentials serving as circuit thresholds. At the time of burn-in, the reference potentials V _ref1 and V _ref2 are set to “H” of the input signals A and B. "or higher than the level V _IH1, V _IH2, or" by or lower than L "level V _IL1, V _IL2, input signals a, irrespective of the level of B, the current flowing through the respective gates of the ECL circuit The route is switched at once. For example, the “H” level V _ref1 (H) and V _ref2 (H) and the “L” level V _ref1 (L) and V _ref2 (L) of each of the reference potentials V _ref1 and V _ref2 are as shown in FIG. V _ref1 (H)> V _IH1 , V _ref1 (L) <V
_{IL1, V ref2 (H)>} V IH2, is set so as to satisfy _{V ref2 (L) <V IL2} . In the normal operation, the reference potentials V _ref1 and V _ref2 are each set to an intermediate level between the “H” level and the “L” level of the input signal as shown in FIG.

As described above, at the time of burn-in, the reference potentials V _ref1 and V _ref2 are changed to the “H” level V _ref1 (H), V
_ref2 (H) or “L” level V _ref1 (L), V _ref2
When set to (L), the current path of the ECL circuit shown in FIG. 18 is switched as shown in Table 4 below.

Table 4 The potential of V _ref2 The potential of V _ref1 Current path _Vref2 (L) _Vref1 (L) P1 _Vref2 (L) _Vref1 (H) P2 _Vref2 (H) _Vref1 (L) P3 _Vref2 (H) _Vref1 (H) P4 As described above, according to the second embodiment, the levels of the reference potentials V _ref1 and V _ref2 are changed to the “H” level V during the burn-in.
_ref1 (H), V _ref2 (H) or “L” level V
_The current path can be switched only by setting _ref1 (L) and _Vref2 (L), and the time required for burn-in can be greatly reduced.

Further, the burn-in method of the second embodiment can be applied to an integrated circuit in which the ECL circuits of FIG. 16 are interconnected in a plurality of stages, similarly to the first embodiment, and all the reference potentials V _ref are applied. , The current paths of all the ECL circuits can be switched at the same time, and the time required for burn-in can be greatly reduced.

In the first embodiment, not all paths can be freely switched. For example, which of the paths connected to the input transistors Q7 _a , Q7 _b , and Q7 _c flows a current depends on the input signals A, B, and C.
Depends on. Therefore, it is still necessary to input a test pattern in order to apply a current to all paths.

The second embodiment has the following restrictions. That is, V _ref1 = V _ref1 (L), V
_ref2 = V _ref2 (H) in some cases. For example, V
_{Assuming that ref1} (L) = − 1.7 V and V _ref2 (H) = − 1.3 V, the potential of the node N1 is V _ref1 (L) −φ in FIG.
= −1.7V−0.8V = −2.5V. Therefore, the bipolar transistor Q15 to which _Vref2 is input
Has a collector potential of -2.5 V and a base potential of V
_ref2 (H) = - 1.3V next, V _BC = -1.3V-
(−2.5 V) = 1.2 V> φ, and the base-collector is turned on in the forward direction. As a result, the current flowing from the base to the collector escapes to the substrate and becomes a substrate current, which can cause problems such as latch-up. In order not to forward bias between the base and collector of the transistor Q15, V _BE = V _ref2 (H) − (V _ref1 (L) −φ) <φ
That is, it is necessary that V _ref1 (L)> V _ref2 (H).
While keeping this constraint, and V _ref1 (L) <V _IH1 , V
_ref2 (H)> V _IH2 to meet, including noise margin, logic amplitude V _IH1 -V _IL1 gate of the ECL circuit, and the V _{IH 2} -V _IL2 to the requirements to be considerably smaller than the φ Become. Otherwise, in Table 2, V _ref1 =
V _ref1 (L), V _ref2 = V _ref2 (H) cannot be set,
The current cannot flow through the path P3.

Next, a first embodiment of the burn-in method according to the second invention will be described with reference to FIGS.
The burn-in method of this embodiment is used when a plurality of ECL circuits shown in FIG. 16 are interconnected. At the time of burn-in, first, complementary outputs of differential switch stages of all ECL circuits, for example, nodes NZ and bar NZ _Are short-circuited, and then the reference potential V _{ref1 is set} to the “H” level V _ref1 (H) or the “L” level V _ref1 (L). Here, the level values V _ref1 (H) and V _ref1 (L) must satisfy V _ref1 (H)> V _IM1 > V _ref1 (L) as shown in FIG. Here, V _IM1 is an intermediate level between “H” level V _IH1 and “L” level V _IL1 .
During normal operation, the reference potential V _ref1 is set to “H” level V _IH1 and “L” level V of the input signal as shown in FIG.
It is set to an intermediate level V _IM1 of _IL1.

The result of the complementary output is shorted to the differential switch stage of all the ECL circuits, the output potentials of all the ECL circuit is an intermediate level V _{IM 1} of "H" level V _IH1 and the "L" level V _IL1 Therefore, the inputs A,
The potentials of B and C are “H” level V _IH1 and “L” level V
It has become an intermediate level V _IM1 of _IL1. At this time, when the reference potential V _ref1 is set to the “H” level V _ref1 (H),
Since the three input signals A, B, and C in FIG. 16 are given the outputs of the preceding ECL circuit, all of them have the reference potential V.
_The potential (V _1M1 ) becomes lower than that of _ref1 , and the current _flows through path P4.
Flows through. On the other hand, the reference potential V _{ref1 is changed} to the “L” level V _ref1.
When set to (L), all three input signals A, B, and C have a potential (V _1M1 ) higher than the reference potential V _ref1 , and all three input signals A, B, and C have the same potential. The current flows equally through the paths P1, P2, P3.

After short-circuiting the complementary output nodes NZ and NZ of the differential switch stages of all the ECL circuits,
By setting the reference potential V _ref1 to the “H” level V _ref1 (H) or the “L” level V _ref1 (L), FIG.
The current path of the gate of the ECL circuit shown in FIG. 6 can be switched as shown in Table 5.

Table 5 V _ref1 potential Current path V _ref1 (L) P1, P2, P3 (equal) V _ref1 (H) P4 As described above, according to this embodiment, the time required for burn-in can be greatly reduced. In addition, by eliminating the need for a test pattern as in the conventional method, a certain degree of burn-in can be performed on the wafer, and waste of expensive packages can be suppressed to some extent.
An expensive pulse generator for inputting a test pattern is not required.

Next, a second embodiment of the burn-in method according to the second invention will be described with reference to FIGS.
The burn-in method of this embodiment is used when a plurality of ECL circuits shown in FIG. 18 are interconnected. At the time of burn-in, first, complementary outputs of the differential switch stages of all the ECL circuits, for example, nodes NZ and NZ are connected. Short-circuited, and then the reference potentials V _ref1 and V _ref2 are set to the respective “H” level V
_ref1 (H), V _ref2 (H), or “L” level V _ref1
(L) and V _ref2 (L). Here, the level values V _ref1 (H), V _ref1 (L), V _ref2 (H), V
_As shown in FIG. 13, _ref2 (L) must satisfy _Vref1 (H)> _VIM1 > _Vref1 and _Vref2 (H)> _VIM2 > _Vref2 (L). Here, V _IM1, V _IM2, respectively "H" level V _IH1 and the "L" level V _IL1 intermediate, and, "H" level V _IH2 and the "L" level V _IL2
The middle level. At the time of normal operation, the reference potential V _ref1, V _{re f2} are respectively set to an intermediate level V _IM1, V _IM2 of the input signal as shown in FIG. 19.

After shorting the complementary output nodes of the differential switch stages of all the ECL circuits, the reference potential V _{ref1 is changed} to the level V
_ref1 (H) or level V _ref1 (L) and the reference potential V _ref2 is set to level V _ref2 (H) or level V
_ref2 (L) to set the ECL shown in FIG.
The current path at the gate of the circuit can be switched as shown in Table 6.

Table 6 The potential of V _ref2 The potential of V _ref1 Current path _Vref2 (L) _Vref1 (L) P1 _Vref2 (L) _Vref1 (H) P2 _Vref2 (H) _Vref1 (L) P3 _Vref2 (H) _Vref1 (H) P4 As described above, it goes without saying that the second embodiment also has the same effect as the first embodiment.

Next, a description will be given of a semiconductor device having an ECL circuit and the like according to the third invention and having a reference potential control circuit for achieving the above-described burn-in method of the present invention. Before that, a reference potential generation circuit for generating a reference potential of the ECL circuit will be described. The reference potential generating circuit is generally configured as shown in FIG. 14 (a) or 14 (b). The reference potential generating circuit shown in FIG. 14A includes a load resistor R having one end grounded, a current source 4 connected to the other end of the load resistor R, a collector grounded, and a base connected to the load resistor R. An npn-type bipolar transistor Q1 connected to the other end, and a reference potential _Vref is generated from the emitter of the transistor Q1. In the reference potential generation circuit shown in FIG. 14B, the transistor Q1 is removed from the reference potential generation circuit shown in FIG.
The reference potential _Vref is taken out from a connection point between the reference current source 4 and the constant current source 4.

The reference potential generating circuits shown in FIGS. 14A and 14B normally generate a reference potential based on a constant potential obtained by a band gap reference circuit. The circuit is configured as shown in FIG. 15, the band-gap referencing lance circuit Widlar constant potential V _M generated by the master bias circuit 40 based on (hereinafter, also referred to as BGR circuit) is sent to the slave bias circuit 42. And the slave bias circuit 42 based on the constant potential V _M 3
One of the reference potential V _ref1, V _ref2, V _CS is generated, these reference potentials _{V re f1, V ref2, V} CS is sent to the ECL circuit 44. The load resistance R of the slave bias circuit 42 is shown in FIG.
4 (a), and corresponds to the slave bias circuit 42.
Potential V _CS , transistor Q _B , and load resistance R
_B corresponds to the constant current source 4 in FIG.

The semiconductor device having the reference potential control circuit according to the third invention switches the level of the reference potential _Vref generated from the reference potential generation circuit between normal operation and burn-in. A first embodiment of a semiconductor device having a reference potential control circuit according to the third invention will be described with reference to the drawings. FIGS. 1A and 1B are conceptual diagrams of a reference potential control circuit of the semiconductor device according to the first embodiment. FIG.
The reference potential control circuits shown in FIGS.
(A) A circuit for directly controlling the reference potential _Vref by drawing one end of a load resistor R of the reference potential generating circuit shown in (a) and (b) to a pad 2 and externally applying an input voltage _VIN to the pad 2. It is.

In a normal operation, the pad 2 is connected to a lead terminal to which a signal of the GND level is applied, so that the input voltage V
_IN is set to the GND level, and the input voltage V _IN is set to V _ref (H) −V _IM or V _ref (L) −V _IM during burn-in.
Set to. Then, during normal operation, the reference potential V _ref becomes V _ref = V _IM , and at burn-in, V _ref = V _IN + V _IM = V _ref (H) or V _ref = V _IN + V _IM = V _ref (L). Here, the resistance value of the load resistor R is R, and the constant current source 4
The constant current If and I _B, the V _BE of the transistor Q1 phi of the burn-in apparatus shown in FIG. 1 (a), V _IM = - a _{(I B · R + φ)} , V in FIG. 1 (b) _IM = −I _B · R V _ref (H) or V _ref (L) indicates a desired “H” level or “L” level of the reference potential V _ref .

FIG. 2 shows a configuration in which the concept shown in FIGS. 1A and 1B is applied to a specific reference potential generating circuit shown in FIG. In FIG. 2, one end of the load resistor R of the slave master circuit 42 is drawn out to the pad 2.

As described above, the load resistance R of the reference voltage generating circuit
Is applied to the pad 2 and an appropriate input voltage V _IN is externally applied to the pad 2 so that the reference potential V _ref can be switched between normal operation and burn-in. V
_ref (H) or V _ref (L) can be provided to the ECL circuit, whereby the time required for burn-in can be reduced.

FIG. 3 shows a modification of the first embodiment.
(A) and (b) show. In this modification, the pad 2 is drawn from a connection point between the load resistor R and the constant current source 4, and the pad 2 is opened during normal operation. At the time of burn-in, the input voltage V _IN
In the device shown in FIG. 3A, it is set to V _ref (H) + φ or V _ref (L) + φ, and in the device shown in FIG. 3B, it is set to V _ref (H) or V _ref (L). Is done.

By doing so, the same effect as that of the first embodiment can be obtained in the burn-in device of the above-mentioned modified example.

According to the modification of FIGS. 3A and 3B, the pad 2 is opened during the normal operation.
There is no need to bond the pad 2 after sealing the CL circuit in the package. Therefore, the number of package pins is reduced,
Costs are reduced.

When this modified example is applied to the specific circuit shown in FIG. 15, the node A of the circuit shown in FIG.

Next, a second embodiment of a semiconductor device having a reference potential control circuit according to the third invention will be described with reference to FIGS. Figure 4 (a), (b) are those showing a concept of the second embodiment, respectively, of FIG 14 (a), the constant current source 4 of the current I _B of the reference potential generating circuit shown in (b) size It is designed to switch the length. The switching of the magnitude of the current is performed by three npn bipolar transistor pairs (Q
_{2 a, Q2 b), (} Q3 a, Q3 b), and (Q
4 _a , Q 4 _b ) and three constant current sources 4 ₁ , 4 ₂ , 4 ₃ . FIG. 4 (a), (b)
In the transistor Q2 _a, commonly connected emitters of Q2 _b is connected to the constant current source 4 _1, transistor Q
3 _a, Q3 commonly connected emitters of _b constant current source 4
Is connected to the _2, commonly connected emitters of the transistors Q4 _a, Q4 _b are connected to the constant current source 4 _3. The collectors of the transistors Q2 _a , Q3 _a , and Q4 _a are grounded, and the collectors of the transistors Q2 _b , Q3 _b , and Q4 _b are commonly connected and connected to one end of a load resistor R. Note that the other end of the load resistor R is grounded. Transistors Q2 _a, Q3 _a, Q4 in _a base of constant potential V _IM, i.e. "H" level to the "L" level and the intermediate level is applied, the transistors Q2 _b, Q3 _b, Q
4 Each potential V ₁ was the base of the _b, V _2, V ₃ is applied. By setting only one of these _three potentials V ₁ , V ₂ , V ₃ to “H” and the other to “L” level, “H”
Only the transistor whose level potential is applied to the base is turned on, and the current of the constant current source connected to this transistor flows through the load resistor R. For example, when only V ₁ is set to “H” and V ₂ and V ₃ are set to “L”, the transistor Q 2 _b among the transistors Q 2 _b , Q 3 _b and Q 4 _b
b only is turned on, a constant current I _B of the constant current source 4 ₁ will flow to the load resistor R. Therefore, the constant current sources 4 ₁ ,
4 _2, 4 ₃ constant current I _B, I _H, if each differently properly configured I _L, by changing the level of the electric potential V _1, V _2, V _3, the level of the reference potential V _ref Desired potential levels V _IM , V _ref (H), and V _ref (L) can be set.

FIG. 5 shows a configuration in the case where the concept shown in FIG. 4A is used for the specific reference potential generating circuit of FIG. Each of the three constant current sources in this case is formed of a series circuit in which an npn transistor and a resistor are connected in series.
For example the constant current source 4 ₁ transistor Q _a and a resistor gamma _B, the constant current source 4 ₂ transistors Q _b and a resistor gamma _H, the constant current source 4
₃ consists of a transistor Q _c resistance γ _L. Here, the current levels of the _three constant current sources 4 ₁ , 4 ₂ , 4 ₃ usually adjust the resistance values γ _B , γ _H , γ _L (if necessary, the transistors Q _a , Q _b , Q _c Adjust the size of the
Can be adjusted.

As described above, the second embodiment can provide the same effects as the first embodiment.

FIG. 6 shows a modification of the second embodiment.
(A) and (b) show. In this modification, FIG.
In the reference electronic control circuit of the semiconductor device shown in (a) and (b), three pairs of bipolar transistors (Q2 _a , Q2
2 _b), the _{(Q3 a, Q3 b),} (Q4 a, Q4 b),
This is replaced with a switch composed of three P-type MOS transistors T ₁ , T ₂ and T ₃ . The potential V applied to the gate of each of the _three transistors T ₁ , T ₂ , T _3
By switching ₁ , V ₂ and V ₃ appropriately, the same effect as in the second embodiment can be obtained. In the above modification, a P-type MOS transistor is used as the switch, but an N-type MOS transistor may be used.
Further, an analog switch in which a P-type MOS transistor and an N-type MOS transistor are connected in parallel may be used.
Further, the switch by the MOS transistor may be inserted at any point in the branched current path, for example, between the bipolar transistor of the constant current source and the resistor, or between the resistor and the power supply V _EE.
Between.

Next, a description will be given of a third embodiment of the semiconductor device provided with the circuit of the reference potential justice according to the third invention with reference to FIGS. FIGS. 7A and 7B show the concept of the third embodiment. The magnitude of the load resistance R of the reference potential generating circuit shown in FIGS. 14A and 14B is switched by a switch. It is like that. As switches, three P-type MOS transistors T ₁ , T ₂ and T ₃ are used. A series circuit consisting of the transistors T ₁ and the load resistance R, a series circuit composed of the transistors T ₂ and the load resistance R _H, the transistor T ₃ and the load resistance R
_L is connected in parallel with a series circuit consisting of
It is connected to the. By appropriately adjusting the potentials V ₁ , V ₂ , and V ₃ applied to the gates of the transistors T ₁ , T ₂ , and T ₃ , current flows only in one of the three series circuits. For example, when V _{1 is set} to V _EE and V ₂ and V ₃ are set to the GND level, only the transistor T ₁ is turned on, and current flows only in the series circuit including the transistor T ₁ and the resistor R. Therefore, by appropriately setting the magnitudes of the three resistors R, _RH , and _RL , the reference potential V _ref can be set to the desired levels V _IM , V _ref (H), and V _ref.
(L).

FIG. 8 shows a configuration in the case where the concept shown in FIG. 7A is used for the specific reference potential generating circuit shown in FIG. 8A also switches the potential of the node A by appropriately setting the potential applied to the gates of the switches T ₁ , T ₂ and T ₃ , as in FIG. _ref1 and _Vref2 can be switched to desired levels.

As described above, the third embodiment can provide the same effects as the first embodiment.

In the third embodiment, a P-type MOS transistor is used as a switch.
Transistors, or a P-type MOS transistor and N
An analog switch in which type MOS transistors are connected in parallel may be used. These switches may be inserted anywhere in the current path, for example, between the resistor and the node A.

Next, referring to FIG. 9, an embodiment of a semiconductor device having an ECL circuit and the like according to the fourth invention and having a reference potential control circuit for achieving the burn-in method of the present invention described above will be described. Will be explained. The semiconductor device of this embodiment is:
Short-circuit means for short-circuiting the complementary output node of the differential switch stage of the gate of the ECL circuit during burn-in, and switching means for switching the reference potential of the ECL circuit between normal operation and burn-in.

FIG. 9 shows a specific example of the short circuit means. In FIG. 9, the complementary output node NZ to be short-circuited and the bar NZ
Connect the source and drain type MOS transistor T _p, connecting the gate to the control line bar BI. At the time of burn-in, the control line bar BI is set to "L" and the P-type MOS
To turn on the transistor T _p, in the normal operation to turn off the transistor T _p to "H" control line bar BI.
By doing so, the complementary output nodes can be short-circuited during burn-in.

The short circuit of the complementary output node at the time of burn-in may be performed as follows. The complementary output node is short-circuited with a metal wiring in advance, and after the burn-in, the metal wiring is cut with a laser or the layer of the metal wiring is chemically removed so that the complementary output node is not short-circuited. The metal wiring may be formed again.

The switching means for switching the reference potential between the time of burn-in and the time of normal operation can be constituted by using the above-described third embodiment of the present invention.

Then, in the embodiment of the fourth invention,
At the time of burn-in, a test pattern is used by first short-circuiting the complementary output nodes of the differential switch stages of all the gates of the ECL circuit by short-circuit means, and then switching the reference potential of the ECL circuit to a desired level by the switching means. Current can flow in all the current paths of the ECL circuit. As a result, the time required for burn-in can be significantly reduced. Further, since the test pattern is not required, burn-in can be performed to some extent on the wafer, waste of an expensive package can be suppressed to some extent, and an expensive pulse generator for inputting a test pattern is not required.

FIG. 24 shows a state in which many ECL circuits shown in FIG. 16 or 18 are arranged on semiconductor substrate 100. One to three reference potentials V _ref1 , V _ref2 , and V _ref3 are supplied to each ECL circuit from the reference potential generation circuit VG. Then, by controlling the reference potential generated from the reference potential generation circuit VG as described in each of the above embodiments, burn-in can be performed on all the ECL circuits on the semiconductor substrate 100 at the same time.

In each of the above embodiments, the present invention is applied to the ECL circuit. However, the present invention is not limited to the ECL circuit.
MOSFET (Metal Oxide) that performs the same operation as L circuit
The present invention can also be applied to Semiconducor Type Field Effect Transistor).

[0077]

As described above, according to the present invention, the time required for burn-in can be greatly reduced.

In particular, when a large number of ECL circuits are provided on a semiconductor substrate, it is conventionally necessary to input an enormous test pattern from a large number of input terminals to the ECL circuits to perform burn-in. Depending on the connection state of the circuit, there is an ECL circuit in which there is little opportunity for a current to flow, so that there is a problem that a long time is required for burn-in.

On the other hand, according to the present invention, burn-in can be performed only by controlling the reference potential supplied to each ECL circuit. Therefore, several types of test patterns may be used, and burn-in can be performed on many ECL circuits simultaneously, so that the time required for burn-in is also reduced. Further, since several types of test patterns are sufficient, burn-in can be performed on the wafer. Therefore, there is no need to waste expensive packages as in the prior art, and no burn-in board or expensive pulse generator is required.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating the concept of a first embodiment of the third invention.

FIG. 2 is a circuit diagram when the concept shown in FIG. 1 is applied to a specific reference potential generation circuit.

FIG. 3 is a circuit diagram showing a modification of the first embodiment of the third invention.

FIG. 4 is a circuit diagram illustrating the concept of a second embodiment of the third invention.

FIG. 5 is a circuit diagram when the concept shown in FIG. 4 is applied to a specific reference potential generation circuit.

FIG. 6 is a circuit diagram showing a modification of the second embodiment of the third invention.

FIG. 7 is a circuit diagram illustrating the concept of a third embodiment of the third invention.

8 is a circuit diagram when the concept shown in FIG. 7 is applied to a specific reference potential generation circuit.

FIG. 9 is a circuit diagram showing a specific example of the short-circuit means according to the fourth invention.

FIG. 10 is an explanatory diagram for explaining a level of a reference potential in the first embodiment of the burn-in method according to the first invention;

FIG. 11 is an explanatory diagram for explaining a level of a reference potential in a second embodiment of the burn-in method according to the first invention;

FIG. 12 is an explanatory diagram illustrating a level of a reference potential in the first embodiment of the burn-in method according to the second invention.

FIG. 13 is an explanatory diagram for explaining a level of a reference potential in a second embodiment of the burn-in method according to the second invention.

FIG. 14 is a circuit diagram illustrating the concept of a reference potential generation circuit.

FIG. 15 is a circuit diagram showing a specific example of a reference potential generation circuit.

FIG. 16 is a circuit diagram illustrating an example of an ECL circuit.

17 is an explanatory diagram illustrating a level of a reference potential of the ECL circuit illustrated in FIG.

FIG. 18 is a circuit diagram showing another example of the ECL circuit.

FIG. 19 is an explanatory diagram illustrating a level of a reference potential of the ECL circuit illustrated in FIG. 18;

FIG. 20 is a graph showing a change with time of the failure rate of the ECL circuit.

FIG. 21 shows a three-input OR using the ECL circuit shown in FIG.
FIG. 4 is a circuit diagram showing an example of a two-stage gate connection circuit.

FIG. 22 is a circuit diagram showing one row of a circuit in which a counting circuit and an inverter are connected to a stage preceding the circuit shown in FIG. 21;

FIG. 23 is a timing chart illustrating operation of the circuit illustrated in FIG. 22;

FIG. 24 is a diagram showing a row in which a number of ECL circuits are arranged on a semiconductor substrate.

[Explanation of symbols]

Strength R load resistance V _ref the reference potential of the second pad 4 constant current source I _B constant current source current

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A 1-312480 (JP, A) JP-A 6-11538 (JP, A) JP-A 5-136680 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G01R 31/26 H01L 21/66

Claims (3)

(57) [Claims] 1. A signal output circuit comprising: a plurality of interconnected signal output circuits; each signal output circuit comprising a differential circuit; comparing an input signal potential of the differential circuit with a reference potential; A short circuit between complementary output nodes of the differential circuit so that an input signal of a subsequent signal output circuit is set to an intermediate level between the maximum level and the minimum level of the input signal. Setting the reference potential higher or lower than the input signal set to the intermediate level. 2. A signal output circuit comprising: a plurality of interconnected signal output circuits; each signal output circuit comprising a differential circuit; in normal operation, an input signal potential of the differential circuit is compared with a reference potential; A semiconductor device that outputs an output signal in accordance with a comparison result, wherein an input signal potential of a signal output circuit of a subsequent stage is changed between a maximum level and a minimum level by short-circuiting between complementary output nodes of the differential circuit. Setting means for setting to an intermediate level; and switching for setting the reference potential to be higher or lower than the input signal potential set to the intermediate level between the normal operation and the burn-in operation. A semiconductor device comprising means. 3. The switching circuit according to claim 2, wherein the switching unit sets the reference potential higher than a maximum level of the input signal potential or lower than a minimum level of the input signal potential. 3. The semiconductor device according to claim 1.