JPH11133103A - Semiconductor integrated circuit having hysteresis - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having hysteresis with a hysteresis width easily measureable in a short time. SOLUTION: A first selector SL1 selects a second test signal TEST2 in accordance with a first test signal TEST1 in measuring, and a transistor MP1 controls a resistance value in accordance with the second test signal TEST2 to generate different reference voltages. A switch SW connects an output node of a comparator COMP to an input end in accordance with the first test signal TEST1 at the time of measuring, and the comparator COMP is set as a voltage follower circuit. This voltage follower circuit outputs different reference voltage as a first and a second threshold voltages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a comparator or a buffer having a hysteresis (hereinafter referred to as a hysteresis comparator or a hysteresis buffer), and more particularly to a measurement of a threshold voltage thereof.

[0002]

2. Description of the Related Art A hysteresis comparator is used in, for example, a semiconductor integrated circuit for a camera or a circuit for monitoring a power supply voltage of a semiconductor integrated circuit for a vehicle. Such a hysteresis comparator has two different threshold voltages. The measurement of whether the potential difference between the two threshold voltages, that is, the hysteresis width is set as designed, has conventionally been performed as follows. First, the input voltage is stepwise increased from 0 V to the power supply voltage Vcc, and the change of the output voltage with respect to this input voltage, that is, the input voltage when the level changes from high level or low level to low level or high level is measured. After this,
The input voltage is reduced stepwise from the power supply voltage Vcc to 0 V, and the change of the output voltage with respect to the input voltage, that is, the input voltage when the level changes from low level or high level to high level or low level is measured. The hysteresis width is obtained from the potential difference between the two input voltages thus measured.

[0003]

In the case of a circuit having a narrow hysteresis width of, for example, 10 mV, the step width of the input voltage must be set to 10 mV to measure the hysteresis width.
Must be set to: Therefore, there is a problem that the number of measurement points increases and the measurement time increases.

In addition, since a special measuring device such as an input voltage generating circuit is required outside the semiconductor integrated circuit for the measurement, the measuring operation is complicated. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor integrated circuit having a hysteresis capable of measuring a hysteresis width easily and in a short time. It is.

[0005]

In a semiconductor integrated circuit having hysteresis according to the present invention, a first or second reference voltage is supplied to a first input terminal, and an input voltage is supplied to a second input terminal. A comparator for comparing these voltages, a reference voltage generating circuit for generating the first or second reference voltage according to an output voltage of the comparator, and a circuit between the second input terminal and the output terminal of the comparator. A switch for connecting the second input terminal and the output terminal according to a first test signal at the time of measurement, and setting the comparator to a voltage follower circuit; and a second test terminal connected to the first input terminal. A second input terminal is connected to the output terminal, and the second input terminal is connected to the second test terminal during measurement according to the first test signal.
A first selector for selecting the test signal of the reference signal, and an output terminal of the selector and the reference voltage generating circuit, which are connected to each other and output the reference signal according to the second test signal output from the selector at the time of measurement. A switching circuit for changing a first or second reference voltage generated by a voltage generation circuit, wherein the first or second reference voltage generated by the reference voltage generation circuit at the time of measurement is passed through the voltage follower circuit. Output from the output terminal as a first or second threshold voltage.

Further, according to the present invention, there is provided a semiconductor integrated circuit having hysteresis, comprising: a first inverter circuit to which an input voltage is supplied; a second inverter circuit connected to an output terminal of the first inverter circuit; A setting that is connected between the output terminal of the first inverter circuit and one of the power supplies, and sets the first threshold voltage or the second threshold voltage in the first inverter circuit according to the output voltage of the second inverter circuit. A circuit, a switch disposed between the input and output terminals of the first inverter circuit, for connecting the input and output terminals in response to a first test signal during measurement, and a first input terminal connected to the second inverter. A second test signal is supplied to a second input terminal of the circuit, an output terminal of the second test signal is connected to the setting circuit, and the second test signal is supplied in response to the first test signal during measurement. Select A selector, wherein the setting circuit sets the first threshold voltage or the second threshold voltage in the first inverter circuit according to the second test signal supplied from the selector at the time of measurement. .

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention, and shows a case where the present invention is applied to a hysteresis comparator. In the hysteresis comparator 10 shown in FIG.
Are connected in series between resistors R1, R2, and R3 for generating a reference voltage between the power supply line 11 to which the reference voltage is supplied and the ground line 12 set to the ground potential GND. The comparator COMP includes PNP transistors P1 and P2, NPN transistors N1 and N2, and a constant current source I1. The emitters of the transistors P1 and P2 are connected to a power supply line 11 via a constant current source I1.
A base of the transistor P1 as a first input terminal is connected to a connection node between the resistors R2 and R3, and an input voltage Vin is supplied to a base of the transistor P2 as a second input terminal. The collector of the transistor P1 is connected to each collector of the transistor N1, and the collector of the transistor P2 is connected to the collector of the transistor N2 and the bases of the transistors N1 and N2. The collector of the transistor P1 is an NPN transistor N
3 connected to the base. The emitter of the transistor N3 is connected to the ground line 12, and the collector is connected to the power line 11 via a resistor R4. An output voltage Vout is output from a connection node (hereinafter referred to as an output node Nout) between the resistor R4 and the collector of the transistor N3.
Is output.

On the other hand, this hysteresis comparator
A circuit for measuring the hysteresis width is included. That is, the second test signal TEST2 is input to the first input terminal A of the first selector SL1, and the second input terminal B
Is connected to the output node Nout. The first selector SL1 selects the first input terminal A or the second input terminal B according to the first test signal TEST1. The output terminal of the first selector SL1 is connected to an inverter circuit IV1.
Through a P-channel MOS transistor (hereinafter referred to as PMO
S) is connected to the gate of MP1. This PM
The source of OSMP1 is connected to the power supply line 11, and the drain is connected to a connection node between the resistors R1 and R2. This PMOS MP1 is connected to the second test signal TE.
It is turned on and off according to ST2, and resistors R1, R2, R3
Changes the reference voltage generated by

The switch SW is connected to the transistor P
2 and the output node Nout. This switch SW is connected to the first test signal TEST
1, is turned on at the time of measurement, connects the output node Nout and the base of the transistor P2, and sets the comparator CO
The MP is operated as a voltage follower circuit (amplifier).

Further, the first input terminal A of the second selector SL2 is connected to the collector of the transistor P2. The output terminal of the second selector SL2 is connected to the output node Nout via the capacitor C1 and to the second input terminal B of the second selector SL2. The second selector SL2 selects the first input terminal A or the second input terminal B according to the first test signal TEST1. When operating the comparator COMP as a voltage follower circuit at the time of measurement, the capacitor C1 adjusts the phase of this circuit to prevent oscillation.

The first and second selectors SL1, SL
2, and the switch SW are configured by, for example, a well-known analog switch. In the above configuration, the normal operation of the hysteresis comparator 10 will be described first with reference to FIG. In this case, the first test signal TE
ST1 is set to the low level. For this reason, the first and second selectors SL1 and SL2 each select the second input terminal B, and the switch SW is off. In this state, the input voltage Vin is changed from 0 V to Vcc · R3 / (R2
When the voltage is swept to + R3) V, the transistor N3 is turned off in this voltage range, and the output voltage Vout becomes a high level. For this reason, since the PMOS MP1 is turned on,
The base voltage of the transistor P1 is Vcc · R3 / (R2 +
R3) V. That is, when the input voltage Vin is Vcc · R3
When / (R2 + R3) V, the voltage becomes the first threshold voltage.

Thereafter, the input voltage Vin is further increased by the power supply voltage V
When sweeping to cc, the transistor N3 is turned on in this voltage range, so that the output voltage Vout becomes low level. Therefore, since the PMOS MP1 is turned off, the base voltage of the transistor P1 becomes Vcc · R3 / (R1 +
R2 + R3) V. When the input voltage Vin is in the range from the power supply voltage Vcc to Vcc · R3 / (R1 + R2 + R3) V, the transistor N3 is turned on, and the output voltage Vout is at a low level, so that the PMOS MP1 is turned off. Therefore, the base voltage of the transistor P1 is Vcc · R3 / (R
1 + R2 + R3) V. That is, when the input voltage Vin is Vcc · R3 / (R1 + R2 + R3) V, the voltage becomes the second threshold voltage.

The input voltage Vin is further swept from this voltage to 0V. In this voltage range, the transistor N3 is turned off, and the output voltage Vout becomes high level.
Therefore, since the PMOS MP1 is turned on, the base voltage of the transistor P1 is Vcc · R3 / (R2 + R3) V
Becomes Here, an ideal comparator is assumed.

On the other hand, at the time of measurement, the first test signal TES
T1 is set to the high level, and the first and second selectors SL
1, SL2 selects the first input terminal A, and the switch SW is turned on. For this reason, the output node Nout and the transistor P are connected to the comparator COMP by the switch SW.
A negative feedback circuit connecting the two bases is formed, and the comparator COMP becomes a voltage follower circuit. In this state, when the second test signal TEST2 is set to a low level, the PMOS MP1 is turned off. Therefore, the reference voltage Vcc · R3 is set by the resistors R1, R2, and R3.
/ (R1 + R2 + R3) is generated, and this reference voltage is supplied to the base of the transistor P1. Comparator C
OMP is a voltage follower circuit,
The base voltage of the transistor P1 and the base voltage of the transistor P2, that is, the voltage of the output node Nout become equal, and the voltage Vcc · R3 / (R1
+ R2 + R3) is output.

When the second test signal TEST2 is set to a high level, the PMOS MP1 is turned on. Therefore, the reference voltage Vcc · R3 /
(R2 + R3) is generated, and this reference voltage is supplied to the base of the transistor P1. The base voltage of the transistor P1 becomes equal to the voltage of the output node Nout, and the voltage Vcc · R3 / (R2 + R3) is output from the output node Nout.

The voltage at the output node when the second test signal TEST2 is set to low level or high level is measured, and the hysteresis width can be obtained from the potential difference between these two measured voltages.

According to the first embodiment, the hysteresis comparator is provided with the PMOS MP1, the first and second selectors SL1 and SL2, the switch SW, and the first and second test signals TEST1 and TEST2 for controlling these. During measurement, the comparator COMP is set to a voltage follower circuit by the first and second selectors SL1 and SL2 and the switch SW, and the reference voltage generated by the resistors R1, R2 and R3 is changed by the PMOS MP1. Therefore, unlike the related art, there is no need to generate an input voltage including a plurality of step voltages for measurement, and two threshold voltages can be measured at high speed only by switching the second test signal TEST2. , Measurement time can be reduced.

Further, the first and second selectors SL1, SL
2. Since the switch SW can be configured by an analog switch having a simple configuration, an increase in chip area can be suppressed.

Further, the output node and the node to which the input voltage Vin is supplied are short-circuited by the switch SW. Therefore, measurement can be performed from a node to which the input voltage Vin is supplied. That is, generally, the output terminal of the comparator is not connected to the pin of the semiconductor integrated circuit, and it is often difficult to directly take out the output signal of the comparator to the outside. However, the node to which the input voltage Vin is supplied is connected to the pin. Have been. Therefore, with the configuration of this embodiment, measurement can be performed from the node to which the input voltage Vin is supplied.

Although FIG. 1 is constituted by a Bi-CMOS circuit, the present invention is not limited to this. All transistors may be constituted by bipolar transistors, or all transistors may be constituted by bipolar transistors. It is.

FIG. 3 shows a second embodiment of the present invention, in which the present invention is applied to a hysteresis buffer. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals.

In the hysteresis buffer 30 shown in FIG. 3, the first inverter circuit IV11 includes a PMOSMP
11 and an N-channel MOS transistor (hereinafter referred to as NM
MN11). These P
The gates of the MOSMP11 and the NMOS MN11 are connected to each other, and an input voltage Vin is supplied to these gates. The source and the substrate of the PMOSMP11 are connected to the power supply line 11, and the drain is the NMOSMN11.
Connected to the drain of The source and the substrate of the NMOS MN11 are connected to the ground wiring GND.

The drains of the PMOS MP11 and NMOS MN11 as the output terminals of the first inverter circuit IV11 are connected to the PMOS MP12, MP13 and NMOS MN1 constituting the second and third inverter circuits IV12 and IV13.
2. Connected to the gate of MN13. The PMOS
The source and the substrate of the MP 12 are connected to the power supply wiring 11, and the drain is connected to the drain of the NMOS MN 12. The source and the substrate of the NMOS MN 12 are connected to the ground wiring 12. The PMOSMP
The source and substrate 13 are connected to the power supply wiring 11,
The drain is connected to the drain of the NMOS MN13. The source and the substrate of the NMOS MN 13 are connected to the ground wiring 12. The first output voltage Vout1 is supplied from the drains of the PMOS MP11 and the NMOS MN11.
And the second output voltage Vout2 is output from the drains of the PMOS MP13 and the NMOS MN13.

The PMOS MP11 and the NMOS MN1
NMOSs MN14 and MN15 for setting hysteresis are connected in series between the drain 1 and the ground wiring 12. That is, the drain of the NMOS MN14 is connected to the drains of the PMOS MP11 and the NMOS MN11, the gate is connected to the power supply wiring 11, and the substrate is connected to the ground wiring 12. The source of the NMOS MN14 is connected to the drain of the NMOS MN15.
The source and the substrate of the OSNN 15 are connected to the ground wiring 12. The NMOSs MN14 and MN15 act as resistors for setting the hysteresis width.

On the other hand, the hysteresis buffer 30
A circuit for measuring the hysteresis width is included. That is, the switch SW1 is connected to the first inverter circuit I
It is connected between the input and output terminals of V1. This switch SW
1 turns on and off according to the first test signal TEST1. Further, the first input terminal A of the selector SL3 is connected to the second input terminal A.
Forming the output terminal of the inverter circuit IV12 of FIG.
The MP12 is connected to the drains of the NMOS MN12, and the second input terminal B is supplied with the second test signal TEST2. The selector SL3 selects the first and second input terminals according to the first test signal TEST1.

Next, the normal operation of the hysteresis buffer 30 shown in FIG. 3 will be described with reference to FIG. In this case, the first test signal TEST1 is at a low level. For this reason, the switch SW1 is turned off and the selector SL
3 selects the first input terminal A. In this state, when the input voltage Vin ranges from 0 V to the first threshold voltage Vth1 at which the output voltage of the first inverter circuit IV1 is inverted, the PMOS MP11, the NMOS MN12, and the MN13 are on, and the NMOS MN15 is off. Also, NMOS
MN14 is always on. Therefore, the first output voltage Vout1 becomes high level, and the second output voltage Vout2 as the inverted signal becomes low level. Since the NMOS MN15 is off, the first threshold voltage Vth1 of the hysteresis buffer 30 is as follows.

Vth1 = Vcc · RN11 / (RP11 + RN11) where RN11 is the on-resistance of the NMOS MN11 and R
P11 is an on-resistance of the PMOS MP11.

When the input voltage Vin becomes higher than the first threshold voltage Vth1, the first inverter circuit IV1 is inverted.
In the range between the first threshold voltage Vth1 and the power supply voltage Vcc,
Since the NMOS MN11, the PMOS MP12, and the MP13 are turned on, the first output voltage Vout1 goes low and the second output voltage Vout2 goes high. PMOSMP12
Is turned on, the NMOS MN15 is also turned on. Therefore, the threshold voltage of the hysteresis buffer 30 becomes the second threshold voltage Vth2 represented by the following equation.

Vth2 = Vcc.RN11. (RP14 + R
N15) / (RP11 ・ (RN11 + RN14 + RN1
5) + RN11 · (RP14 + RN15)) Here, RN11, RN14, and RN15 are each N
ON resistance of MOSMN11, MN14, MN15, RP
Reference numeral 11 denotes an on-resistance of the PMOS MP11.

When the input voltage Vin ranges from the power supply voltage Vcc to the second threshold voltage Vth2, the NMOS MN11 and the PMOS
MP12 and MP13 are on and the first output voltage Vou
t1 remains at the low level, and the second output voltage Vout2 remains at the high level.

When the input voltage Vin is equal to the second threshold voltage Vth2 and 0
In the range of V, PMOSMP11, NMOSMN12,
MN13 turns on and NMOS MN15 turns off. Therefore, the first output voltage Vout1 is at a high level, and the second output voltage Vout2 is at a low level. Since the NMOS MN15 is turned off, the threshold voltage of the hysteresis buffer 30 becomes the first threshold voltage Vth1.

On the other hand, at the time of measurement, the first test signal TES
T1 is set to the high level, the switch SW is turned on,
The selector SL3 selects the second input terminal B. When the switch SW is turned on, the first inverter circuit IV
1 receives negative feedback, and the first inverter circuit IV1 outputs a circuit threshold voltage. In this state, when the second test signal TEST2 is set to low level, the NMOSMN
15 turns off. Therefore, the first output voltage Vout1
Becomes the first threshold voltage Vth1.

When the second test signal TEST2 is set to a high level, the NMOS MN15 is turned on. Therefore, the first output voltage Vout1 is equal to the second threshold voltage Vth2
Becomes The hysteresis width can be obtained from the potential difference between the first and second threshold voltages Vth1 and Vth2.

According to the second embodiment, the selector SL3 and the switch SW1 and the first and second test signals TEST1 and TEST1 for controlling the selector SL3 and the switch SW1 are provided in the hysteresis buffer.
ST2 is provided, the switch SW1 applies negative feedback to the first inverter circuit IV11 during measurement to set a circuit threshold, and the selector SL3 sets the NMOS MN14 and MN15.
, And the first and second threshold voltages Vth1 and Vth2 are set. Therefore, unlike the related art, there is no need to generate an input voltage composed of a plurality of step voltages for measurement, and the second test signal TE
Since the two threshold voltages can be measured at high speed only by switching ST2, the measurement time can be reduced.

Further, since the switch SW1 and the selector SL3 are constituted by analog switches having a simple structure, an increase in chip area can be prevented. Of course, various modifications can be made without departing from the spirit of the present invention.

[0036]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit having a hysteresis capable of measuring the hysteresis width easily and in a short time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform chart shown for explaining the operation of FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a waveform chart shown for explaining the operation of FIG. 3;

[Explanation of symbols]

Reference Signs List 10: hysteresis comparator, 30: hysteresis buffer, R1, R2, R3: resistor, COMP: comparator, MP1, MP11 to MP13: P-channel MOS transistor, MN11 to MN15: N-channel MOS transistor, P1, P2: PNP transistor, N1 ... N3: NPN transistor, SL1, SL2: first and second selectors, SL3 ... selector, SW, SW1 ... switch, IV11 to IV13 ... first to third inverter circuits, TEST1, TEST2 ... first, second Test signal.

Claims (5)

[Claims] A first input terminal is supplied with a first or second reference voltage, a second input terminal is supplied with an input voltage, and a comparator for comparing these voltages; and an output voltage of the comparator. Depending on the first or second
A reference voltage generating circuit for generating a reference voltage between the second input terminal and the output terminal of the comparator, the second input terminal and the output terminal being connected in response to a first test signal during measurement; A switch for setting the comparator to a voltage follower circuit; a second test signal supplied to a first input terminal; a second input terminal connected to the output terminal; A first selector for selecting the second test signal in accordance with the test signal of the above, and a second selector connected between an output terminal of the selector and the reference voltage generation circuit and output from the selector during measurement. A switching circuit for changing the first or second reference voltage generated by the reference voltage generating circuit in accordance with the test signal of (1), wherein the first or second signal generated by the reference voltage generating circuit at the time of measurement is provided. 2. A semiconductor integrated circuit having hysteresis, wherein a second reference voltage is output from the output terminal as the first or second threshold voltage via the voltage follower circuit. 2. A capacitor for preventing oscillation of the voltage follower circuit, and a second selector for connecting the capacitor between a current path of the comparator and the output terminal according to the second test signal. 2. The method according to claim 1, further comprising:
A semiconductor integrated circuit having the hysteresis described above. 3. The circuit according to claim 1, wherein said reference voltage generating circuit comprises a resistor circuit, and said switching circuit comprises a transistor connected in parallel to a part of said resistor circuit.
A semiconductor integrated circuit having the hysteresis described above. 4. A first inverter circuit to which an input voltage is supplied, a second inverter circuit connected to an output terminal of the first inverter circuit, and an output terminal of the first inverter circuit, A setting circuit that is connected between power supplies and sets a first threshold voltage or a second threshold voltage in the first inverter circuit according to an output voltage of the second inverter circuit; A switch disposed between the output terminals and connecting the input and output terminals in response to a first test signal during measurement; a first input terminal connected to an output terminal of the second inverter circuit; A second test signal is supplied to the input end,
An output terminal connected to the setting circuit, comprising a selector for selecting the second test signal in accordance with the first test signal during measurement, wherein the setting circuit supplies the second test signal from the selector during measurement. 2. A semiconductor integrated circuit having hysteresis, wherein the first threshold voltage or the second threshold voltage is set in the first inverter circuit according to a test signal of (2). 5. The setting circuit includes a plurality of transistors connected between an output terminal of the first inverter circuit and a ground, and an output terminal of the selector is connected to a gate of one of the transistors. 5. A semiconductor integrated circuit having hysteresis according to claim 4, wherein: