JP2004079841A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can identify the category determination result by a WT even in its mold state. <P>SOLUTION: A mode register set circuit 2 outputs a mode register enable signal in accordance with the input from a category determination circuit 1a and input of an address control signal Add and a mode register set activation signal MRS. When the mode register enable signal is at a H level, the value of CL(CAS latency) or BL (burst length) in the default state is changed. Whether or not the value of CL or BL is changed from the default is output from an output terminal used for the usual operation of the semiconductor integrated circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit on which a wafer test is performed.
[0002]
[Prior art]
The quality test of a semiconductor integrated circuit is generally performed in two stages, a wafer test (WT) and a final test (FT).
[0003]
First, WT is performed on a semiconductor integrated circuit in a wafer state.
In the WT, in order of quality, several categories such as category 1 (pass in a normal WT), category 2 (not pass in a normal WT, but pass if certain test conditions are relaxed),. are categorized. Here, the semiconductor integrated circuits classified into category 1 are referred to as "normal products", and the semiconductor integrated circuits classified into category 2 and below are referred to as "ranked products".
[0004]
After WT, FT is performed on the molded (resin-sealed) semiconductor integrated circuit. However, the molded semiconductor integrated circuit has not been able to identify the category determination result by the WT until now.
[0005]
Therefore, in the conventional FT, first, all the semiconductor integrated circuits are tested at the level of the “normal product”, and the semiconductor integrated circuits that do not reach the level of the “normal product” are next tested at the level of the “ranked product”. Had been tested.
[0006]
[Problems to be solved by the invention]
If the category determination result by the WT can be identified in the FT, the FT is performed at the “normal product” level for the semiconductor integrated circuit of the category 1 and, in parallel, the semiconductor integrated circuit of the category 2 and below is performed. It is considered that by performing FT at the level of "ranked product", the productivity of the semiconductor integrated circuit can be improved.
[0007]
However, in the conventional semiconductor integrated circuit, the category determination result by the WT cannot be identified in the FT, and the FT has to be performed a plurality of times as described above, so that the productivity of the semiconductor integrated circuit is reduced. There was a problem.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of identifying a category determination result by a WT even in a molded state.
[0009]
[Means for Solving the Problems]
A semiconductor integrated circuit according to the present invention blows a fuse element according to a result of a category classification of a semiconductor integrated circuit by a wafer test, so that a category determining circuit that determines a category of the semiconductor integrated circuit, A category identification circuit for identifying a category of the molded semiconductor integrated circuit by changing a predetermined value of the semiconductor integrated circuit when the determination is made, and an output terminal used for normal operation of the semiconductor integrated circuit. Is output to
[0010]
According to another aspect of the present invention, a category determining circuit for determining a category of a semiconductor integrated circuit by blowing a fuse element according to a result of a category classification of the semiconductor integrated circuit by a wafer test, and a predetermined node of the category determining circuit And a current detection terminal for identifying a category of the molded semiconductor integrated circuit by monitoring a value of a current flowing through the semiconductor integrated circuit.
[0011]
Preferably, the category determination circuit includes: a fuse element having one end connected to the first power supply potential line; a resistance element connected between the other end of the fuse element and the second power supply potential line; A first transfer gate circuit, which is connected between the other end of the fuse element and the first output node, and is brought into a non-conductive state and a conductive state in response to activation and deactivation of the first control signal, respectively; Including.
[0012]
More preferably, the category determination circuit includes: an input terminal to which a predetermined potential is applied; a current detection terminal connected to an output pin of the semiconductor integrated circuit; a plurality of fuse elements having one end connected to the input terminal; A plurality of transistors connected between the other ends of the fuse elements and the second power supply potential line, the gate terminals of which are connected to the second power supply potential line; And a transistor having a gate terminal connected to the line of the second power supply potential.
[0013]
More preferably, the category identification circuit receives the activation of the second control signal and inverts the input signal, and receives the output signal of the inverter element as an input, and activates and deactivates the first control signal. And a latch circuit for holding an output signal of the first or second transfer gate circuit.
[0014]
According to another aspect of the present invention, there is provided a semiconductor integrated circuit having a test mode and a normal mode as operation modes, wherein a fuse element is blown according to a result of a category classification of the semiconductor integrated circuit by a wafer test. A category determining circuit for determining a category of the integrated circuit; and a category identifying circuit for adjusting an output according to a category determining result of the category determining circuit in a test mode, thereby identifying a category of the molded semiconductor integrated circuit. .
[0015]
According to another aspect of the present invention, there is provided a semiconductor integrated circuit having a test mode and a normal mode as operation modes, wherein a fuse element is blown according to a result of a category classification of the semiconductor integrated circuit by a wafer test. A category determination circuit for determining a category of the integrated circuit; and a current detection terminal for identifying a category of the molded semiconductor integrated circuit by monitoring a value of a current flowing through a predetermined node of the category determination circuit in a test mode. .
[0016]
Preferably, the category determination circuit includes: a fuse element having one end connected to the first power supply potential line; a resistance element connected between the other end of the fuse element and the second power supply potential line; One electrode is connected to the other end of the fuse element, and has a first conductivity type having a first conductivity type that is turned on and off according to activation and deactivation of a test mode signal input from a gate terminal, respectively. And an inverter element which receives the other electrode of the first transistor having the first conductivity type as an input and inverts an input signal, and an output terminal of the inverter element and a line between the second power supply potential and the inverter element. A second transistor of a second conductivity type, which is connected and becomes nonconductive and conductive according to activation and deactivation of a test mode signal input from a gate terminal, respectively.
[0017]
Therefore, according to the present invention, the category of the semiconductor integrated circuit by the wafer test can be identified in the molded state by blowing the fuse element according to the result of the category classification of the semiconductor integrated circuit by the wafer test.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.
[0019]
[Embodiment 1]
FIG. 1 is a schematic block diagram showing a characteristic portion of a semiconductor integrated circuit according to a first embodiment of the present invention.
[0020]
The characteristic portion of the semiconductor integrated circuit according to the first embodiment shown in FIG. 1 has a configuration in which a category determination circuit 1a according to the present invention is added to the mode register set circuit 2. Mode register set circuit 2 outputs a mode register enable signal according to the input from category determination circuit 1a and the input of address control signal Add and mode register set activation signal MRS.
[0021]
FIG. 2 is a circuit diagram showing a specific circuit configuration of a characteristic portion of the semiconductor integrated circuit according to the first embodiment shown in FIG.
[0022]
The characteristic portion of the semiconductor integrated circuit according to the first embodiment shown in FIG. 2 includes a category determination circuit 1a and a mode register set circuit 2.
[0023]
The category determination circuit 1a is connected between the fuse 10a connected between the power supply node and the node N1, the resistor 11a connected between the node N1 and the ground node, and connected between the node N1 and the node N3. It includes a transfer gate 12a and an inverter 13a for inverting an input to one of the transfer gates 12a.
[0024]
Transfer gate 12a conducts when power-on reset signal / POR is at L level, and electrically connects node N1 to node N3. When power-on reset signal / POR is at H level, transfer gate 12a is turned off, and electrically disconnects nodes N1 and N3.
[0025]
The mode register set circuit 2 includes an inverter 20 connected between the input terminal of the address control signal Add and the node N2, a transfer gate 21 connected between the nodes N2 and N3, and one of the transfer gates 21. And a latch circuit 23 connected between nodes N3 and N4.
[0026]
Transfer gate 21 conducts when power-on reset signal / POR is at H level, and electrically connects node N2 to node N3. When power-on reset signal / POR is at L level, transfer gate 21 is turned off, and electrically disconnects nodes N2 and N3.
[0027]
If the WT classifies the semiconductor integrated circuit into, for example, category 2 (ranked product), the semiconductor integrated circuit of the first embodiment blows the fuse 10a of the category determination circuit 1a.
[0028]
FIG. 3 is a timing chart when the fuse 10a of the category determination circuit 1a is blown in the semiconductor integrated circuit of the first embodiment.
[0029]
At time t1, the external power supply is turned on, and the external power supply potential exVCC goes to the H level as shown in FIG. As shown in (b), the power-on reset signal / POR is at the L level even after the external power is turned on until time t3. Since the fuse 10a is blown, the node N1 remains at the L level even after the external power is turned on, as shown in FIG.
[0030]
Since power-on reset signal / POR is at L level until time t3 even after external power is turned on, transfer gate 12a electrically connects node N1 to node N3. Therefore, the node N3 goes low, and at time t2, the node N4 goes high via the latch circuit 22, as shown in (d). When the node N4 goes high, the mode register enable signal goes high.
[0031]
As described above, when the fuse 10a is blown, the mode register enable signal becomes H level when the external power is turned on. When the mode register enable signal goes high, the value of CL (CAS latency) or BL (burst length), which is the default state, can be changed.
[0032]
On the other hand, as shown in (e), the inverter 20 is activated by setting the mode register set activation signal MRS to the H level at the time t5. Further, as shown in (b), the power-on reset signal / POR goes to the H level from time t3 to t4, so that the transfer gate 21 electrically connects the nodes N2 and N3.
[0033]
Therefore, since the address control signal Add is at the L level as shown in (f), the nodes N2 and N3 are at the H level. Since the node N3 is at the H level, the node N4 goes to the L level via the latch circuit 22 at the time t6 as shown in (d). When the node N4 goes low, the mode register enable signal goes low.
[0034]
As described above, after setting the address control signal Add to L level, for example, and setting the mode register set activation signal MRS to H level, the mode register enable signal becomes L level. When the mode register enable signal goes low, the values of CL and BL can be returned to the default values.
[0035]
FIG. 4 is a timing chart when the fuse 10a of the category determination circuit 1a is not blown in the semiconductor integrated circuit of the first embodiment.
[0036]
At time t1, the external power supply is turned on, and the external power supply potential exVCC goes to the H level as shown in FIG. As shown in (b), the power-on reset signal / POR is at the L level even after the external power is turned on until time t3. Since the fuse 10a is not blown, the node N1 goes to the H level from the time t1 to the time t2 after the external power is turned on, as shown in FIG.
[0037]
Since power-on reset signal / POR is at L level until time t3 even after external power is turned on, transfer gate 12a electrically connects node N1 to node N3. Therefore, the node N3 goes to the H level, and the node N4 remains at the L level even after the external power is turned on via the latch circuit 22, as shown in FIG. Since the node N4 remains at the L level, the mode register enable signal also remains at the L level.
[0038]
As described above, when the fuse 10a is not blown, the mode register enable signal remains at the L level even after the external power is turned on. Since the mode register enable signal remains at the L level, the values of CL and BL remain at the default values.
[0039]
On the other hand, when the mode register set activation signal MRS is set to the H level at time t5 after setting the address control signal Add to the L level, for example, the mode register enable signal is set to the L level as in the case where the fuse 10a is blown. Become. Since the mode register enable signal remains at the L level, the values of CL and BL remain at the default values.
[0040]
Therefore, whether or not the fuse 10a is blown can be known by checking whether or not the value of CL or BL has been changed from the default value. However, it is assumed that the values of CL and BL have not been returned to the default values by the mode register set activation signal MRS. As described above, the fuse 10a is blown when the semiconductor integrated circuit is classified into, for example, the category 2 (low rank product) by the WT.
[0041]
Whether or not the value of CL or BL has been changed from the default value is known by reading the values of CL and BL from the signal waveform of the output terminal that reads the data of the memory cell in synchronization with the clock signal input from the outside. be able to.
[0042]
By checking whether or not the value of CL or BL has been changed from the default value as described above, it is possible to identify whether or not the semiconductor integrated circuit has been classified into, for example, category 2 by the WT. Thus, whether or not the value of CL or BL has been changed from the default value can be identified in the molded semiconductor integrated circuit.
[0043]
As described above, according to the first embodiment, by checking whether the value of CL or BL has been changed from the default value, it is possible to identify the category determination result by the WT of the molded semiconductor integrated circuit. .
[0044]
[Embodiment 2]
FIG. 5 is a schematic block diagram showing a characteristic portion of the semiconductor integrated circuit according to the second embodiment of the present invention.
[0045]
The characteristic part of the semiconductor integrated circuit according to the second embodiment shown in FIG. 5 has a configuration in which the category judgment circuit 1b according to the present invention is added to the output buffer 3. The semiconductor integrated circuit according to the second embodiment enters the test mode from the normal mode when identifying the category determination result of the WT. Output buffer 3 outputs a signal to output pin DQ in accordance with an input from category determination circuit 1b and an input from read data bus pair RD and / RD.
[0046]
FIG. 6 is a circuit diagram showing a specific circuit configuration of the category determination circuit 1b.
The category determination circuit 1b includes a fuse 10b connected between the power supply node and the node N5, a resistor 11b connected between the node N5 and the ground node, and a connection between the input node of the inverter 14b and the node N5. An N-channel MOS transistor 12b connected to receive a test mode signal from a gate terminal; a P-channel MOS transistor 13b connected between an output node of inverter 14b and a ground node to receive a test mode signal from a gate terminal; Includes an inverter 14b connected to the output node N6 of the category determination circuit 1b. The output node N6 of the category determination circuit 1b is connected to the output buffer 3, as shown in FIG.
[0047]
If the WT classifies the semiconductor integrated circuit into, for example, category 2 (ranked product), the semiconductor integrated circuit according to the second embodiment blows the fuse 10b of the category determination circuit 1b.
[0048]
FIG. 7 is a table showing how the level of the node N6 changes depending on the test mode signal when the fuse 10b is blown and when the fuse 10b is not blown.
[0049]
When the fuse 10b is blown, the node N5 goes to L level.
Here, when the category determination circuit 1b is in the normal mode, the test mode signal is at L level, the N-channel MOS transistor 12b is turned off, and the P-channel MOS transistor 13b is turned on. For this reason, the output node N6 of the category determination circuit 1b is connected to the ground node and goes to L level.
[0050]
When the category determination circuit 1b is in the test mode, the test mode signal goes high, the N-channel MOS transistor 12b is turned on, and the P-channel MOS transistor 13b is turned off. Therefore, output node N6 of category determination circuit 1b attains H level via inverter 14b.
[0051]
On the other hand, when fuse 10b is not blown, node N5 is at H level.
[0052]
Here, when the category determination circuit 1b is in the normal mode, the test mode signal is at L level, the N-channel MOS transistor 12b is turned off, and the P-channel MOS transistor 13b is turned on. For this reason, the output node N6 of the category determination circuit 1b is connected to the ground node and goes to L level.
[0053]
When the category determination circuit 1b is in the test mode, the test mode signal goes high, the N-channel MOS transistor 12b is turned on, and the P-channel MOS transistor 13b is turned off. Therefore, the output node N6 of the category determination circuit 1b goes low through the inverter 14b.
[0054]
That is, as shown in FIG. 7, when the category determination circuit 1b is in the normal mode, the node N6 is at the L level regardless of whether the fuse 10b is blown or not. On the other hand, when the category determination circuit 1b is in the test mode, the node N6 is at the H level when the fuse 10b is blown, and at the L level when the fuse 10b is not blown.
[0055]
Output buffer 3 receiving an input from output node N6 of category determination circuit 1b outputs a corresponding signal to output pin DQ when node N6 is at H level. On the other hand, when the node N6 is at the L level, the output buffer 3 stops outputting the output from the output pin DQ.
[0056]
Therefore, whether or not the fuse 10b is blown can be known by checking whether or not the output is output from the output pin DQ of the output buffer 3 in the test mode. As described above, the fuse 10b is blown when the semiconductor integrated circuit is classified as, for example, Category 2 (rank-defective product) by the WT.
[0057]
That is, by checking whether or not an output is output from the output pin DQ of the output buffer 3 in the test mode, it is possible to identify whether or not the semiconductor integrated circuit has been classified into, for example, category 2 by the WT. Whether or not an output is output from the output pin DQ of the output buffer 3 in the test mode can be identified in the molded semiconductor integrated circuit.
[0058]
As described above, according to the second embodiment, the category determination result by the WT of the molded semiconductor integrated circuit is identified by checking whether an output is output from the output pin DQ of the output buffer 3 in the test mode. be able to.
[0059]
[Embodiment 3]
FIG. 8 is a schematic block diagram showing a characteristic portion of the semiconductor integrated circuit according to the third embodiment of the present invention.
[0060]
The characteristic portion of the semiconductor integrated circuit according to the third embodiment shown in FIG. 8 has a configuration in which the category determination circuit 1b according to the present invention is added to the ACT command decoder 4. The semiconductor integrated circuit according to the third embodiment enters the test mode from the normal mode when identifying the category determination result of the WT. The ACT command decoder 4 outputs an ACT command signal according to the input from the category determination circuit 1b and the input of each of the control signals CLK, / CS, RAS, CAS, WE, and Add.
[0061]
The specific circuit configuration of category determination circuit 1b has been described with reference to FIG. 6 of the second embodiment, and will not be repeated here.
[0062]
If the WT classifies the semiconductor integrated circuit into, for example, category 2 (ranked product), the semiconductor integrated circuit according to the third embodiment blows the fuse 10b of the category determination circuit 1b.
[0063]
How the level of the node N6 changes depending on the test mode signal when the fuse 10b is blown and when the fuse 10b is not blown is as described in FIG. 7 of the second embodiment.
[0064]
That is, as shown in FIG. 7, when the category determination circuit 1b is in the normal mode, the node N6 is at the L level regardless of whether the fuse 10b is blown or not. On the other hand, when the category determination circuit 1b is in the test mode, the node N6 is at the H level when the fuse 10b is blown, and at the L level when the fuse 10b is not blown.
[0065]
ACT command decoder 4 receiving an input from output node N6 of category determination circuit 1b outputs a corresponding ACT command signal when node N6 is at H level. On the other hand, when the node N6 is at the L level, the ACT command decoder 4 does not output the ACT command signal.
[0066]
Therefore, by checking whether or not the ACT command signal is output from the ACT command decoder 4 in the test mode, it is possible to know whether or not the fuse 10b is blown. As described above, the fuse 10b is blown when the semiconductor integrated circuit is classified as, for example, Category 2 (rank-defective product) by the WT.
[0067]
That is, by checking whether or not an ACT command signal is output from the ACT command decoder 4 in the test mode, it is possible to identify whether or not the semiconductor integrated circuit has been classified into, for example, category 2 by the WT. Whether or not the ACT command signal is output from the ACT command decoder 4 in the test mode can be identified in the molded semiconductor integrated circuit.
[0068]
As described above, according to the third embodiment, by checking whether or not the ACT command signal is output from the ACT command decoder 4 in the test mode, it is possible to identify the category determination result by the WT of the molded semiconductor integrated circuit. Can be.
[0069]
[Embodiment 4]
FIG. 9 is a schematic block diagram showing a characteristic portion of a semiconductor integrated circuit according to a fourth embodiment of the present invention.
[0070]
The characteristic portion of the semiconductor integrated circuit according to the fourth embodiment shown in FIG. 9 has a configuration in which the category determination circuit 1b according to the present invention is added to the input buffer 5. The semiconductor integrated circuit according to the fourth embodiment enters the test mode from the normal mode when determining the WT category identification result. Input buffer 5 outputs an internal row address strobe signal intRAS in response to an input from category determination circuit 1b and an input of external row address strobe signal exRAS.
[0071]
The specific circuit configuration of category determination circuit 1b has been described with reference to FIG. 6 of the second embodiment, and will not be repeated here.
[0072]
When the semiconductor integrated circuit is classified by WT as, for example, category 2 (degraded product), the semiconductor integrated circuit of the fourth embodiment blows fuse 10b of category determining circuit 1b.
[0073]
How the level of the node N6 changes depending on the test mode signal when the fuse 10b is blown and when the fuse 10b is not blown is as described in FIG. 7 of the second embodiment.
[0074]
That is, as shown in FIG. 7, when the category determination circuit 1b is in the normal mode, the node N6 is at the L level regardless of whether the fuse 10b is blown or not. On the other hand, when the category determination circuit 1b is in the test mode, the node N6 is at the H level when the fuse 10b is blown, and at the L level when the fuse 10b is not blown.
[0075]
Input buffer 5 receiving an input from output node N6 of category determination circuit 1b outputs a corresponding internal row address strobe signal intRAS when node N6 is at H level. On the other hand, when node N6 is at L level, input buffer 5 does not output internal row address strobe signal intRAS.
[0076]
Therefore, whether the fuse 10b is blown can be known by checking whether the internal row address strobe signal intRAS of the input buffer 5 is output in the test mode. As described above, the fuse 10b is blown when the semiconductor integrated circuit is classified as, for example, Category 2 (rank-defective product) by the WT.
[0077]
That is, by checking whether or not the internal row address strobe signal intRAS of the input buffer 5 is output in the test mode, it is possible to identify whether or not the semiconductor integrated circuit is classified into, for example, category 2 by the WT. Whether or not the internal row address strobe signal intRAS of the input buffer 5 is output in the test mode can be identified even in the molded semiconductor integrated circuit.
[0078]
As described above, according to the fourth embodiment, by checking whether or not internal row address strobe signal intRAS of input buffer 5 is output in the test mode, the category determination result by the WT of the molded semiconductor integrated circuit is identified. can do.
[0079]
[Embodiment 5]
In the first embodiment, when the fuse 10a of the category determination circuit 1a is blown, the output terminal (corresponding to the node N3) of the category determination circuit 1a goes low. On the other hand, when the fuse 10a of the category determination circuit 1a is not blown, the output terminal of the category determination circuit 1a goes high.
[0080]
Therefore, when the fuse 10a of the category determination circuit 1a is blown, almost no current flows through the output terminal of the category determination circuit 1a, and when the fuse 10a of the category determination circuit 1a is not blown, the output of the category determination circuit 1a is output. It is assumed that current flows through the terminal.
[0081]
In the second to fourth embodiments, when the fuse 10b of the category determination circuit 1b is blown in the test mode, the output terminal (corresponding to the node N6) of the category determination circuit 1b goes high. On the other hand, when the fuse 10b of the category determination circuit 1b is not blown in the test mode, the output terminal of the category determination circuit 1a becomes L level.
[0082]
Therefore, when the fuse 10b of the category determination circuit 1b is blown in the test mode, current flows to the output terminal of the category determination circuit 1b, and when the fuse 10b of the category determination circuit 1b is not blown in the test mode, the category determination is performed. It is estimated that almost no current flows through the output terminal of the circuit 1b.
[0083]
Therefore, in the first embodiment, whether the fuse 10a is blown can be known by monitoring the value of the current flowing to the output terminal of the category determination circuit 1a. In the second to fourth embodiments, whether the fuse 10b is blown can be known by monitoring the value of the current flowing to the output terminal of the category determination circuit 1b in the test mode. As described in the first to fourth embodiments, the fuses 10a and 10b are blown when the semiconductor integrated circuit is classified into, for example, the category 2 (ranked product) by the WT.
[0084]
That is, by monitoring the value of the current flowing through the output terminal of the category determination circuit 1a or the category determination circuit 1b in the test mode, it is possible to identify whether the semiconductor integrated circuit is classified into, for example, category 2 by the WT. . Whether a current flows through the output terminals of the category determination circuits 1a and 1b can be identified even in the molded semiconductor integrated circuit.
[0085]
As described above, according to the fifth embodiment, by monitoring the value of the current flowing through the output terminal of the category determination circuit 1a or the category determination circuit 1b in the test mode, the category of the molded semiconductor integrated circuit by the WT is monitored. The judgment result can be identified.
[0086]
Embodiment 6
FIG. 10 is a circuit diagram showing a characteristic portion of a semiconductor integrated circuit according to a sixth embodiment of the present invention.
[0087]
The features of the semiconductor integrated circuit according to the sixth embodiment shown in FIG. 10 include a plurality of fuses 60-1 to 60-n and a plurality of transistors 61-1 to 61 used for an IF (Interface) test of the semiconductor integrated circuit. -N, 62.
[0088]
Fuse 60-k and transistor 61-k (k = 1 to n) are connected in series between node N7 and the ground node. Transistor 62 is connected between node N7 and a ground node. The transistors 61-1 to 61-n and the transistor 62 are connected in parallel to each other with respect to the node N7, and function as high resistance elements by connecting the gate terminal to the ground node. One of the lines of the node N7 is connected to the output pin DQ, and applies a voltage from the other of the lines of the node N7.
[0089]
When the WT classifies the semiconductor integrated circuit into, for example, category 2 (ranked product), the semiconductor integrated circuit according to the sixth embodiment blows at least one of the fuses 60-1 to 60-n. The number of fuses 60-1 to 60-n to be blown can be determined depending on which category the semiconductor integrated circuit is classified into. By blowing at least one of the fuses 60-1 to 60-n, when a voltage is applied from the other of the lines of the node N7, a current value flowing from one of the lines of the node N7 to the output pin DQ changes.
[0090]
Therefore, by monitoring the value of the current flowing from one of the lines of the node N7 to the output pin DQ, it is possible to know whether the fuses 60-1 to 60-n are blown. As described above, the fuses 60-1 to 60-n are blown when the WT classifies the semiconductor integrated circuit into, for example, category 2 (ranked product).
[0091]
That is, by monitoring the value of the current flowing from one of the lines of the node N7 to the output pin DQ, it is possible to identify whether or not the semiconductor integrated circuit is classified into, for example, category 2 by the WT. Whether a current flows from one terminal of the node N7 to the output pin DQ can be identified in the molded semiconductor integrated circuit.
[0092]
As described above, according to the sixth embodiment, by monitoring the value of the current flowing from one terminal of node N7 to output pin DQ, it is possible to identify the category determination result by the WT of the molded semiconductor integrated circuit. it can.
[0093]
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0094]
【The invention's effect】
As described above, according to the present invention, the category of a semiconductor integrated circuit by a wafer test can be identified in a molded state by blowing a fuse element in accordance with the result of the category classification of a semiconductor integrated circuit by a wafer test. .
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a characteristic portion of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific circuit configuration of a characteristic portion of the semiconductor integrated circuit according to the first embodiment shown in FIG.
FIG. 3 is a timing chart in the case where the fuse 10a of the category determination circuit 1a is blown in the semiconductor integrated circuit of the first embodiment.
FIG. 4 is a timing chart in the case where the fuse 10a of the category determination circuit 1a is not blown in the semiconductor integrated circuit according to the first embodiment;
FIG. 5 is a schematic block diagram showing a characteristic portion of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram showing a specific circuit configuration of a category determination circuit 1b.
FIG. 7 is a table showing how the level of a node N6 changes depending on the test mode signal when the fuse 10b is blown and when the fuse 10b is not blown.
FIG. 8 is a schematic block diagram showing a characteristic portion of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 9 is a schematic block diagram showing a characteristic portion of a semiconductor integrated circuit according to a fourth embodiment of the present invention.
FIG. 10 is a circuit diagram showing a characteristic portion of a semiconductor integrated circuit according to a sixth embodiment of the present invention.
[Explanation of symbols]
1a, 1b Category determination circuit, 2 mode register set circuit, 3 output buffer, 4 ACT command decoder, 5 input buffer, 10a, 10b, 60-1 to 60-n fuse, 11a, 11b resistor, 12a, 21 transfer gate, 12b N-channel MOS transistor, 13b P-channel MOS transistor, 13a, 14b, 20, 22 inverter, 23 latch circuit, 61-1 to 61-n, 62 IF test transistor.

Claims (8)

A category determination circuit that determines a category of the semiconductor integrated circuit by blowing a fuse element according to a result of the category classification of the semiconductor integrated circuit by the wafer test;
A category identification circuit that identifies a category of the molded semiconductor integrated circuit by changing a predetermined value of the semiconductor integrated circuit when the category determination circuit determines that the category is a predetermined category;
The semiconductor integrated circuit, wherein a result of the change of the predetermined value is output to an output terminal used for a normal operation of the semiconductor integrated circuit. A category determination circuit that determines a category of the semiconductor integrated circuit by blowing a fuse element according to a result of the category classification of the semiconductor integrated circuit by the wafer test;
A semiconductor integrated circuit comprising: a current detection terminal for identifying a category of the molded semiconductor integrated circuit by monitoring a value of a current flowing through a predetermined node of the category determination circuit. The category determination circuit includes:
A fuse element having one end connected to a first power supply potential line;
A resistance element connected between the other end of the fuse element and a line of a second power supply potential;
A first transfer gate circuit that is connected between the other end of the fuse element and a first output node, and that is turned off and on according to activation and deactivation of a first control signal, respectively; The semiconductor integrated circuit according to claim 1, comprising: The category determination circuit includes:
An input terminal to which a predetermined potential is applied,
The current detection terminal connected to an output pin of the semiconductor integrated circuit;
A plurality of fuse elements having one end connected to the input terminal;
A plurality of transistors connected between the other end of each of the plurality of fuse elements and a line of a second power supply potential, and having a gate terminal connected to the line of the second power supply potential;
3. The semiconductor integrated circuit according to claim 2, further comprising a transistor connected between said output terminal and a second power supply potential line, and a transistor having a gate terminal connected to said second power supply potential line. The category identification circuit includes:
An inverter element for inverting an input signal in response to activation of the second control signal;
A second transfer gate circuit that receives an output signal of the inverter element as an input, and is turned on and off in response to activation and deactivation of a first control signal, respectively;
3. The semiconductor integrated circuit according to claim 1, further comprising: a latch circuit that holds an output signal of the first or second transfer gate circuit. 4. A semiconductor integrated circuit having a test mode and a normal mode as operation modes,
A category determining circuit that determines a category of the semiconductor integrated circuit by blowing a fuse element according to a result of a category classification of the semiconductor integrated circuit by a wafer test;
A category identification circuit that adjusts an output according to a category determination result of the category determination circuit in the test mode to identify a category of the molded semiconductor integrated circuit. A semiconductor integrated circuit having a test mode and a normal mode as operation modes,
A category determining circuit that determines a category of the semiconductor integrated circuit by blowing a fuse element according to a result of a category classification of the semiconductor integrated circuit by a wafer test;
And a current detection terminal for identifying a category of the molded semiconductor integrated circuit by monitoring a value of a current flowing through a predetermined node of the category determination circuit in the test mode. The category determination circuit includes:
A fuse element having one end connected to a first power supply potential line;
A resistance element connected between the other end of the fuse element and a line of a second power supply potential;
One electrode is connected to the other end of the fuse element, and has a first conductivity type that becomes conductive and nonconductive according to activation and deactivation of a test mode signal input from a gate terminal, respectively. One transistor,
An inverter element having the other electrode of the first transistor having the first conductivity type as an input and inverting an input signal;
It is connected between the output terminal of the inverter element and the line of the second power supply potential, and becomes a non-conductive state and a conductive state, respectively, in response to activation and deactivation of the test mode signal input from a gate terminal. The semiconductor integrated circuit according to claim 6, further comprising: a second transistor having a second conductivity type.

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