CN114627945B

CN114627945B - eFuse memory cell and eFuse system

Info

Publication number: CN114627945B
Application number: CN202210511773.0A
Authority: CN
Inventors: 谌敏飞; 罗伟绍; 李建
Original assignee: Hangzhou Jinghua Microelectronics Co ltd
Current assignee: Hangzhou Jinghua Microelectronics Co ltd
Priority date: 2022-05-12
Filing date: 2022-05-12
Publication date: 2023-06-09
Anticipated expiration: 2042-05-12
Also published as: CN114627945A

Abstract

Embodiments of the present disclosure relate to an eFuse memory cell and eFuse system. The eFuse memory cell includes an eFuse resistance, a reference resistance, a first input circuit configured to allow a first current to flow through the eFuse resistance and a second current to flow through the reference resistance if the reset signal is a low level signal, and a latch circuit further configured to trigger the latch circuit to refresh an output if the reset signal is a first pulse signal; the latch circuit is configured to refresh and maintain the first output signal of the first output terminal at a high level or a low level and refresh and maintain the second output signal of the second output terminal at an opposite level to the first output signal depending on a magnitude relation between the first current and the second current after being triggered. According to this scheme, hardware power consumption can be reduced, and the circuit configuration can be simplified.

Description

eFuse memory cell and eFuse system

Technical Field

Embodiments of the present disclosure relate generally to the field of semiconductor devices and, more particularly, to an eFuse memory cell and eFuse system.

Background

eFuses (electrically programmable fuses) belong to one-time program (OTP) memories, and compared with other OTP memories such as fuses and laser fuses, eFuses have the advantages of small occupied area, good process compatibility, no need of additional equipment auxiliary blowing and the like, so that eFuses are increasingly widely applied.

In conventional eFuse memory cells, both the sensing and retention of data by eFuses consumes current. However, under deep submicron process conditions, the power consumption design requirements of the chip are higher and higher, so it is very necessary to reduce the power consumption of the OTP circuit.

Disclosure of Invention

In response to the foregoing, the present disclosure provides an eFuse memory cell and eFuse system that enable hardware power consumption to be reduced and circuit structure to be simplified.

According to a first aspect of the present disclosure, there is provided an eFuse memory cell comprising an eFuse resistor, a reference resistor, a first input circuit and a latch circuit, the eFuse resistor having a first resistance value if unblown and a second resistance value greater than the first resistance value if blown; the resistance value of the reference resistor is between the first resistance value and the second resistance value; the first input circuit including a first input for receiving a reset signal and configured to allow a first current to flow through the eFuse resistor and a second current to flow through the reference resistor if the reset signal is a low level signal, the first current and the second current being inversely proportional to the resistance of the eFuse resistor and the reference resistor, respectively, and the first input circuit being further configured to trigger the latch circuit to refresh an output if the reset signal is a first pulse signal; the latch circuit includes a first output terminal and a second output terminal and is configured to maintain a first output signal of the first output terminal at a high level or a low level depending on a magnitude relation between the first current and the second current and maintain a second output signal of the second output terminal at a level opposite to the first output signal after being triggered.

According to a second aspect of the present disclosure, there is provided an eFuse system comprising sequential logic circuitry, an eFuse memory array comprising a plurality of eFuse memory cells, the plurality of eFuse memory cells being eFuse memory cells as claimed in any of claims 1 to 10; each timing logic circuit comprises a reset signal generation circuit, wherein the output end of the reset signal generation circuit is connected with the first input end of the corresponding eFuse memory unit so as to generate a first pulse signal for the eFuse memory unit; the output sampling circuit is coupled to the first and second outputs of each eFuse memory cell to sample a difference between the first and second output signals of each eFuse memory cell.

In some embodiments, the first current is greater than the second current if the eFuse resistance is unblown, and the second current is greater than the first current if the eFuse resistance is blown.

In some embodiments, the latch circuit is configured to refresh and maintain the first output signal of the first output terminal at a high level and the second output signal of the second output terminal at a low level if the eFuse resistor is not blown, and refresh and maintain the first output signal of the first output terminal at a low level and the second output signal of the second output terminal at a high level if the eFuse resistor is blown after being triggered.

In some embodiments, a second input circuit is also included, the second input circuit including a second input for receiving a programming enable signal, and the second input circuit is configured to allow the eFuse to be resistance blown if the programming enable signal is a second pulse signal.

In some embodiments, the second input circuit includes a first NMOS device (M1) having a gate connected to the second input terminal, a source connected to ground, and a drain connected to the second terminal of the eFuse resistor.

In some embodiments, the first input circuit includes a second NMOS device and a third NMOS device, gates of the second NMOS device and the third NMOS device are both connected to the first input terminal, sources of the second NMOS device and the third NMOS device are both grounded, and a drain of the second NMOS device is connected to the first output terminal, and a drain of the third NMOS device is connected to the second output terminal.

In some embodiments, the first input circuit further includes a fourth PMOS device and a fifth PMOS device, wherein gates of the fourth PMOS device and the fifth PMOS device are each connected to the first input terminal, sources of the fourth PMOS device and the fifth PMOS device are each connected to a supply voltage, and a drain of the fourth PMOS device is connected to the first end of the eFuse resistor, and a drain of the fourth PMOS device is connected to the first end of the reference resistor.

In some embodiments, the latch circuit includes a sixth PMOS device, a seventh PMOS device, an eighth NMOS device, and a ninth NMOS device, where gates of the sixth PMOS device and the eighth NMOS device are each connected to the second output, drains of the sixth PMOS device and the eighth NMOS device are each connected to the first output, a source of the sixth PMOS device is connected to the second end of the eFuse resistor, a source of the eighth NMOS device is grounded, gates of the seventh PMOS device and the ninth NMOS device are each connected to the first output, drains of the seventh PMOS device and the ninth NMOS device are each connected to the second output, a source of the seventh PMOS device is connected to the second end of the reference resistor, and a source of the ninth NMOS device is grounded.

In some embodiments, the first pulse signal has a pulse width between 0.5ns and 4 ns.

In some embodiments, the second pulse signal has a pulse width between 5 mus and 500 mus.

In some embodiments, each sequential logic circuit sequential logic further includes a programming enable signal generating circuit having an output coupled to a second input of a corresponding eFuse memory cell to generate a second pulse signal for the eFuse memory cell.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements.

FIG. 1 illustrates a schematic diagram of a conventional eFuse memory cell 100.

FIG. 2 illustrates a timing diagram of the operation of the conventional eFuse memory cell 100 illustrated in FIG. 1.

Fig. 3 illustrates a schematic structure of an eFuse memory cell 300 in accordance with an embodiment of the present disclosure.

Fig. 4 illustrates a timing diagram of the operation of eFuse memory cell 300 illustrated in fig. 3.

Fig. 5 illustrates a schematic diagram of an eFuse system 500 in accordance with an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a sequential logic circuit 600 according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As described above, in conventional eFuse memory cells, both the sensing and retention of data by eFuses require a drain current. However, under deep submicron process conditions, the power consumption design requirements of the chip are higher and higher, so it is very necessary to reduce the power consumption of the OTP circuit.

To at least partially address one or more of the above problems and other potential problems, example embodiments of the present disclosure present an eFuse memory cell that includes an eFuse resistor, a reference resistor, a first input circuit, and a latch circuit, the eFuse resistor having a first resistance value if unblown and a second resistance value greater than the first resistance value if blown; the resistance value of the reference resistor is between the first resistance value and the second resistance value; the first input circuit including a first input for receiving a reset signal and configured to allow a first current to flow through the eFuse resistor and a second current to flow through the reference resistor if the reset signal is a low level signal, the first current and the second current being inversely proportional to the resistance of the eFuse resistor and the reference resistor, respectively, and the first input circuit being further configured to trigger the latch circuit to refresh an output if the reset signal is a first pulse signal; the latch circuit includes a first output terminal and a second output terminal and is configured to maintain a first output signal of the first output terminal at a high level or a low level depending on a magnitude relation between the first current and the second current and maintain a second output signal of the second output terminal at a level opposite to the first output signal after being triggered. In this way, hardware power consumption can be reduced, and the circuit configuration can be simplified.

FIG. 1 illustrates a schematic structural diagram of a conventional eFuse memory cell 100, and FIG. 2 illustrates a timing diagram of the operation of the conventional eFuse memory cell 100 illustrated in FIG. 1. As shown in FIG. 1, the conventional eFuse memory cell 100 includes an eFuse resistor, an NMOS device M, a first current source 101, a second current source 102, an output sampling circuit 103, and a switch 104. It should be appreciated that eFuse resistances differ in resistance values before and after blowing, having a first resistance value in the unblown case and a second resistance value greater than the first resistance value in the blown case, typically less than 160 ohms, and greater than or equal to 10000 ohms. In general, when a programming current (e.g., about 10 mA) passes through an eFuse resistance for a period of 9 to 200 microseconds, then the eFuse resistance may be considered to be blown. The change in resistance of the eFuse resistor before and after blowing may exist as a variable for circuit trimming. In eFuse memory cell 100, if eFuse resistance is not blown, output signal OUT of the eFuse memory cell is set to a high level, i.e., "1", and if eFuse resistance is blown, output signal OUT of the eFuse memory cell is set to a low level, i.e., "0".

In eFuse memory cell 100, NMOS device M is turned on with the programming enable signal BURN_EN being a pulse signal, thereby allowing programming current (about 10 mA) to flow through the eFuse resistance, thereby enabling programming of the eFuse resistance. The first current source 101 is used to generate a current of, for example, about 20 μa, intended to cause a current of about 20 μa to flow through the eFuse resistor without the eFuse resistor blowing, which causes the voltage at node C (i.e., the drain voltage of the NMOS device M) to be high. However, the presence of a current of 20 μA of the first current source 101 may not only cause the voltage at node C to be high if the eFuse resistance is not blown, but may also cause the voltage at node C to be high if the eFuse resistance is blown. Accordingly, in eFuse memory cell 100, a second current source 102 is also included and switch 104 is also controlled with a RESET signal RESET. The second current source 102 is used to generate a current of, for example, about 400 μA, intended such that the voltage at node C may go low in the event that eFuse resistance is blown. Specifically, as shown in the system power-up and refresh output phases of FIG. 2, if the RESET signal RESET is a pulse signal to close switch 104 in the event that the eFuse resistance is not blown, 400 μA-20 μA of current flows through the blown eFuse resistance, and the voltage at node C remains high because the resistance of the unblown eFuse resistance is low (i.e., the voltage across the eFuse resistance is low). In addition, as shown in the post-programming refresh output stage of FIG. 2, if the RESET signal RESET is a pulse signal to close switch 104 in the event that the eFuse resistance has been blown, then 400 [ mu ] A-20 [ mu ] A of current also flows through the blown eFuse resistance, and the voltage at node C goes low because the resistance of the blown eFuse resistance is high (i.e., the voltage across the eFuse resistance is high). Output sampling circuit 103 may be implemented based on a register that triggers when a RESET signal RESET closes switch 104 to sample the voltage at node C, thereby enabling the output signal OUT of eFuse memory cell 100 to remain high or low.

As can be seen, such a conventional eFuse memory cell 100 needs to consume a current of 20 μa at all times, and also needs to consume a pull-down current of 400 μa in a state where the RESET signal RESET is a pulse signal, so that its overall power consumption is high. Moreover, eFuse memory cell 100 also needs to include a first current source and a second current source (which is typically implemented as a mirrored current source) that occupy a large area in the actual circuit, especially if each eFuse memory cell is equipped with such a current source in an eFuse system, which results in a very large area of the eFuse system. In addition, additional circuit hardware (e.g., output sampling circuit 103) is also required to design these current inputs, and thus the cost is also high. In addition, in eFuse memory cell 100, the output signal OUT is not continuously maintained and requires a RESET signal RESET to be re-used to refresh it once a disturbance occurs. On the other hand, since the resistance value after eFuse resistance burn-out is not exactly equal to 10000 ohms, it is also possible to erroneously sample the voltage at node C as VDD when the supply voltage VDD changes.

FIG. 3 illustrates a schematic diagram of a structure of an eFuse memory cell 300 that may overcome various disadvantages of the conventional eFuse memory cell 100 above in accordance with embodiments of the present disclosure.

As shown in FIG. 3, eFuse memory cell 300 may include eFuse resistor 301, reference resistor RREF 302, first input circuit 303, and latch circuit 304.

eFuse resistor 301 has a first resistance value if unblown and a second resistance value greater than the first resistance value if blown. As mentioned before, typically the first resistance value is less than 160 ohms and the second resistance value is greater than or equal to 10000 ohms. In general, eFuse resistor 301 may be considered to be blown when there is a programming current (e.g., about 10 mA) through eFuse resistor 301 for a period of 9 to 200 microseconds.

In this disclosure, to enable the blowing of eFuse resistor 301, eFuse memory cell 300 may further include a second input circuit 305 for triggering the programming of eFuse resistor 301, such as by allowing a programming current to be applied across eFuse resistor 305 to blow the eFuse resistor. The second input circuit 305 may include a second input terminal for receiving the BURN-in enable signal BURN_EN. Second input circuit 305 is configured to allow eFuse resistor 305 to be blown if write enable signal BURN_EN is a second pulse signal. The pulse width of the second pulse signal may be between 5 mus and 500 mus, for example, may be selected to be 10 mus, so as to ensure that the programming time of the eFuse resistor is not too short to blow the eFuse resistor, and the difference between the resistance values before and after programming is not sufficiently significant because of too long. In the embodiment shown in FIG. 3, second input circuit 305 includes a first NMOS device M1, the gate of the first NMOS device M1 is connected to the second input terminal, the source of the first NMOS device M1 is grounded, and the drain of the first NMOS device is connected to the second terminal of the eFuse resistor. In FIG. 3, when BURN_EN is the second pulse signal and RESET is low, M1 and M4 are both on, and a programming current is flowing through eFuse resistor 301, thereby enabling programming of the eFuse resistor.

The resistance value of the reference resistor RREF 302 is between the above first and second resistance values, which may be 1600 ohms, for example.

The first input circuit 303 comprises a first input for receiving a RESET signal RESET. The first input circuit 303 is configured to allow a first current to flow through the eFuse resistor 301 and to allow a second current to flow through the reference resistor RREF 302 if the RESET signal RESET is a low level signal. For example, in some embodiments, as shown in fig. 3, the first input circuit 303 includes a fourth PMOS device M4 and a fifth PMOS device M5, where gates of the fourth PMOS device M4 and the fifth PMOS device M5 are each connected to the first input terminal, sources of the fourth PMOS device M4 and the fifth PMOS device M5 are each connected to the power supply voltage VDD, and a drain of the fourth PMOS device is connected to the first terminal of the eFuse resistor 301, and a drain of the fourth PMOS device M4 is connected to the first terminal of the reference resistor RREF. According to this embodiment, when RESET is a low signal, both M4 and M5 are turned on, thereby allowing a first current to pass through eFuse resistor 301, the first current being approximately the resistance of VDD/eFuse resistor, and allowing a second current to pass through reference resistor RREF, the second current being approximately the resistance of VDD/reference resistor RREF. It can be seen that the first current and the second current are inversely proportional to the resistance values of the eFuse resistance and the reference resistance, respectively. Since the first resistance value when eFuse resistor 301 is unblown is less than the second resistance value when blown, the first current is greater than the second current if eFuse resistor 301 is unblown and the second current is greater than the first current if eFuse resistor 301 is blown.

In the present disclosure, the first input circuit 303 is further configured to trigger the latch circuit 302 to refresh the output if the RESET signal RESET is the first pulse signal. The pulse width of the first pulse signal may be between 0.5ns and 4ns, and in practical use, since the smaller the first pulse signal, the smaller the power consumption, the better the pulse width of the first pulse signal is selected, for example, 2ns is selected as an example only. For example, in the embodiment shown in fig. 3, the first input circuit 303 may include a second NMOS device M2 and a third NMOS device M3, where gates of the second NMOS device M2 and the third NMOS device M3 are connected to the first input terminal, sources of the second NMOS device M2 and the third NMOS device M3 are grounded, and a drain of the second NMOS device M2 is connected to the first output terminal OUTP, and a drain of the third NMOS device M3 is connected to the second output terminal OUTN. According to this embodiment, if the RESET signal RESET is the first pulse signal, both M4 and M5 are turned off, and M2 and M3 are turned on, thereby triggering the latch circuit 304 to change its output state.

Latch circuit 304 includes a first output terminal and a second output terminal. For example, in the embodiment shown in fig. 3, the first output terminal may be used to output the output signal OUTP (hereinafter, the first output terminal will be referred to as the first output terminal OUTP for convenience of description), and the second output terminal may be used to output the output signal OUTN (hereinafter, the second output terminal will be referred to as the second output terminal OUTN for convenience of description). The latch circuit 304 is configured to refresh and maintain the first output signal OUTP at a high level or a low level depending on a magnitude relation between the first current and the second current, and refresh and maintain the second output signal OUTN at a level opposite to the first output signal OUTP after being triggered. For example, in the embodiment of fig. 3, the latch circuit may include a sixth PMOS device M6, a seventh PMOS device M7, an eighth NMOS device M8, and a ninth NMOS device M9, where gates of the sixth PMOS device M6 and the eighth NMOS device M9 are each connected to the second output terminal OUTN, drains of the sixth PMOS device M6 and the eighth NMOS device M8 are each connected to the first output terminal OUTP, a source of the sixth PMOS device is connected to the second terminal of the eFuse resistor 301, a source of the eighth NMOS device M8 is grounded, gates of the seventh PMOS device M7 and the ninth NMOS device M9 are each connected to the first output terminal OUTP, drains of the seventh PMOS device M7 and the ninth NMOS device M9 are each connected to the second output terminal OUTN, a source of the seventh PMOS device M7 is connected to the second terminal of the reference resistor 302, and a source of the ninth NMOS device M9 is grounded. In these embodiments, after being triggered, latch circuit 304 causes the first output terminal OUTP to follow the high voltage at node a faster, thereby refreshing and maintaining the first output signal OUTP of the first output terminal at a high level, and the second output signal OUTN of the second output terminal at an opposite low level, since the resistance value of eFuse resistor 301 is less than the resistance value of reference resistor RREF 302, if eFuse resistor 301 is not blown. On the other hand, if eFuse resistor 301 is blown, since the resistance value of eFuse resistor 301 is greater than the resistance value of reference resistor RREF 302, the first current flowing through eFuse resistor 301 is less than the second current flowing through reference resistor RREF 302, thereby causing second output OUTN to follow the high level voltage at node B faster, thereby refreshing and maintaining the second output signal OUTN of the second output at a high level and the first output signal OUTP of the first output at an opposite low level.

During the power-up phase of the system as shown in fig. 4, the first output signal OUTP and the second output signal OUTN may each be one of the power supply voltage VDD and the ground voltage GND, but it cannot be determined whether they are actually VDD or GND, and thus are identified by a double cross symbol "XX" in fig. 4 to indicate that the corresponding signals are currently in an unstable output state.

During the refresh output phase as shown in FIG. 4, eFuse resistor 301 has not yet been blown, and thus the resistance of eFuse resistor 301 is now less than the resistance of reference resistor RREF 302. After the RESET signal RESET triggers the latch circuit 304 with the first pulse signal and returns to a low level, the first output terminal OUTP follows the high level voltage at node a faster because the first current flowing through the eFuse resistor 301 is greater than the second current flowing through the reference resistor RREF 302, whereby the latch circuit 304 refreshes and maintains the first output signal OUTP of the first output terminal at a high level and the second output signal OUTN of the second output terminal at an opposite low level.

During the EFUSE programming phase as shown in FIG. 4, the programming enable signal BURN_EN receives a second pulse signal having a pulse width between 5 μs and 500 μs, thereby causing eFuse resistor 301 to be blown.

During the post-programming refresh phase as shown in FIG. 4, eFuse resistor 301 has been blown, so that the resistance of eFuse resistor 301 is now greater than the resistance of reference resistor RREF 302. After the RESET signal RESET triggers the latch circuit 304 with the first pulse signal and returns to a low level, the second output terminal OUTN follows the high level voltage at node B faster because the first current flowing through the eFuse resistor 301 is less than the second current flowing through the reference resistor RREF 302, whereby the latch circuit 304 refreshes and maintains the second output signal OUTN of the second output terminal at a high level and the first output signal OUTP of the first output terminal at an opposite low level.

As shown in fig. 4, after the Efuse resistor is programmed, if the system is powered up again after power-off, the second output signal OUTN of the second output terminal may remain at a high level and the first output signal OUTP may remain at a low level after being refreshed by the RESET signal.

As can be appreciated from FIG. 4, in eFuse memory cell 300, the quiescent current is 0. For example, during the refresh output phase, after the RESET signal RESET changes from the first pulse signal to a low level again, M4, M5 are turned on, so the power supplies at node a and node B are both VDD. During this phase, since the RESET signal RESET is 0, M2 and M3 do not conduct current to GND. In addition, since the bus_en=0 during this stage, M1 also does not conduct current to GND. Further, since outp=vdd during this phase, M9 is on, M7 is off, and no current flows from node B to GND. On the other hand, since outn=0 during this phase, M7 is on and M9 is off, so that no quiescent current flows from node a to GND. It follows that during this phase, no current goes from VDD to GND, so the static power consumption is 0. Similarly, it can be determined that no quiescent current reaches GND from VDD during the post-programming refresh output phase, and thus the quiescent power consumption is also 0.

Therefore, by adopting the means, the static current of the eFuse memory cell can be kept close to 0, so that the static power consumption of the eFuse memory cell is greatly reduced, and the hardware power consumption of the whole cell is greatly reduced. In addition, by adopting the means, special current sources are not required to be arranged for maintaining current, additional circuit hardware such as registers and the like are not required to be arranged for reading data, and the data can be realized by only using a plurality of MOS devices. In addition, the present embodiment also has higher reliability because the latch circuit is used to hold and read out data.

Fig. 5 illustrates a schematic diagram of an eFuse system 500 in accordance with an embodiment of the present disclosure. As shown in FIG. 5, the eFuse system 500 includes a plurality of sequential logic circuits 501, an eFuse memory array 502, and an output sampling circuit 503.

eFuse memory array 502 includes a plurality of eFuse memory cells, which may be eFuse memory cell 300 described above in connection with FIG. 3 or other eFuse memory cells developed based on the aspects of the present disclosure.

Output sampling circuit 503 is coupled to the first and second outputs of each eFuse memory cell to sample the difference between the first and second output signals of each eFuse memory cell.

Each of the timing logic circuits 501 is configured to generate a RESET signal RESET and a programming enable signal bumn_en according to a first control signal and a second control signal provided thereto, respectively, so as to implement programming and output refresh of a corresponding eFuse memory cell connected thereto.

Fig. 6 shows a schematic diagram of a sequential logic circuit 600 according to an embodiment of the present disclosure. In the embodiment shown in FIG. 6, sequential logic circuit 600 (i.e., sequential logic circuit 501 shown in FIG. 5) includes a reset signal generation circuit 601, the output of which is coupled to a first input of a corresponding eFuse memory cell to generate a first pulse signal for the eFuse memory cell. As shown in fig. 6, the reset signal generation circuit 601 may include a delay circuit, an inverter (e.g., a nand gate), and an and gate. The delay circuit may be adapted to generate an ultra-short pulse output signal, i.e. the aforementioned first pulse signal having a pulse width of between 0.5ns and 4ns, when the first control signal generates a rising edge. The delay circuit may be implemented using a variety of known implementations of delay circuits. For example, in some embodiments, the delay circuit may be implemented by CMOS and/or BJT transistors, such as PMOS and NMOS transistors.

As shown in FIG. 6, sequential logic circuit 600 may further include a programming enable signal generation circuit 602, an output of programming enable signal generation circuit 602 being coupled to a second input of a corresponding eFuse memory cell to generate a second pulse signal for the eFuse memory cell. In the embodiment shown in fig. 6, the programming enable signal generating circuit 602 is implemented by a buffer circuit, and the programming control signal can be converted into the burn_en signal through the conversion of the second control signal. In some embodiments, by sequentially providing each sequential logic circuit 600 with a second control signal, the sequential logic circuits may be controlled to sequentially input a programming enable signal to each eFuse memory cell in eFuse memory array 502 on a bit-by-bit basis, thereby reducing the overall disposable current of the eFuse system. For example, if a 10-bit signal is burned at a time, a current exceeding 100mA will be consumed at a time of 10 mus, which is a high requirement for the circuit layout. However, in the present disclosure, by the current being successively programmed, it is made possible to always control the current consumption to around 10mA, so that an excessive load is not imposed on the power supply module of the eFuse system.

In this disclosure, since the hardware consumption of each eFuse memory cell is relatively smaller than conventional, more eFuse memory cells may be integrated in an eFuse system, which may further save costs.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An eFuse system includes a plurality of sequential logic circuits, an eFuse memory array, and an output sampling circuit,

the eFuse memory array includes a plurality of eFuse memory cells, each eFuse memory cell including an eFuse resistor, a reference resistor, a first input circuit and a latch circuit,

the eFuse resistor having a first resistance value if unblown and a second resistance value greater than the first resistance value if blown;

the resistance value of the reference resistor is between the first resistance value and the second resistance value;

the first input circuit including a first input for receiving a reset signal and configured to allow a first current to flow through the eFuse resistor and a second current to flow through the reference resistor if the reset signal is a low level signal, the first current and the second current being inversely proportional to the resistance values of the eFuse resistor and the reference resistor, respectively, and the first input circuit being further configured to trigger the latch circuit to refresh an output if the reset signal is a first pulse signal when no current flows through the eFuse resistor and the reference resistor;

the latch circuit includes a first output terminal and a second output terminal, and is configured to refresh and maintain a first output signal of the first output terminal at a high level or a low level depending on a magnitude relation between the first current and the second current, and refresh and maintain a second output signal of the second output terminal at a level opposite to the first output signal after the reset signal triggers the latch circuit with the first pulse signal and the reset signal changes back to a low level signal;

a second input circuit including a second input for receiving a programming enable signal, and configured to allow the eFuse resistor to be blown if the programming enable signal is a second pulse signal;

each timing logic circuit comprises a reset signal generation circuit, wherein the output end of the reset signal generation circuit is connected with the first input end of the corresponding eFuse memory unit so as to generate a first pulse signal for the eFuse memory unit;

the output sampling circuit is connected with the first output end and the second output end of each eFuse memory unit to sample the difference value between the first output signal and the second output signal of each eFuse memory unit;

and wherein the plurality of sequential logic circuits are configured to input programming enable signals to the plurality of eFuse memory cells sequentially, bit by bit;

the timing logic of each timing logic circuit further comprises a programming enabling signal generating circuit, wherein the output end of the programming enabling signal generating circuit is connected with the second input end of the corresponding eFuse storage unit so as to generate a second pulse signal for the eFuse storage unit;

the first input circuit comprises a second NMOS device and a third NMOS device, wherein the grid electrodes of the second NMOS device and the third NMOS device are connected with the first input end, the source electrodes of the second NMOS device and the third NMOS device are grounded, the drain electrode of the second NMOS device is connected with the first output end, and the drain electrode of the third NMOS device is connected with the second output end;

the first input circuit further comprises a fourth PMOS device and a fifth PMOS device, wherein gates of the fourth PMOS device and the fifth PMOS device are connected with the first input end, sources of the fourth PMOS device and the fifth PMOS device are connected with a power supply voltage, a drain electrode of the fourth PMOS device is connected with the first end of the eFuse resistor, and a drain electrode of the fourth PMOS device is connected with the first end of the reference resistor.

2. The eFuse system of claim 1, wherein the first current is greater than the second current if the eFuse resistance is unblown, and the second current is greater than the first current if the eFuse resistance is blown.

3. The eFuse system of claim 2 wherein the latch circuit is configured to refresh and maintain the first output signal of the first output terminal at a high level and the second output signal of the second output terminal at a low level if the eFuse resistance is unblown after being triggered and refresh and maintain the first output signal of the first output terminal at a low level and the second output signal of the second output terminal at a high level if the eFuse resistance is blown.

4. The eFuse system of claim 1, wherein the second input circuit includes a first NMOS device, wherein a gate of the first NMOS device is connected to the second input terminal, a source of the first NMOS device is grounded, and a drain of the first NMOS device is connected to a second terminal of the eFuse resistor.

5. The eFuse system of claim 1, wherein the latch circuit includes a sixth PMOS device, a seventh PMOS device, an eighth NMOS device, and a ninth NMOS device, wherein gates of the sixth PMOS device and the eighth NMOS device are each connected to the second output, drains of the sixth PMOS device and the eighth NMOS device are each connected to the first output, a source of the sixth PMOS device is connected to the second end of the eFuse resistor, a source of the eighth NMOS device is grounded, gates of the seventh PMOS device and the ninth NMOS device are each connected to the first output, drains of the seventh PMOS device and the ninth NMOS device are each connected to the second output, a source of the seventh PMOS device is connected to the second end of the reference resistor, and a source of the ninth NMOS device is grounded.

6. The eFuse system of claim 1, wherein the second pulse signal has a pulse width between 5 μs and 500 μs.

7. The eFuse system of claim 1, wherein the first pulse signal has a pulse width between 0.5ns and 4 ns.