DE102006017480B4 - Circuit arrangement with a non-volatile memory cell and method - Google Patents

Abstract

Circuit arrangement with a non-volatile memory cell, comprising
A symmetrically constructed comparator (3) comprising a self-holding function and connected in a differential current path connecting a supply voltage terminal (9) to a reference potential terminal (8),
- The non-volatile memory cell (10), which is connected in a first branch (35) of the differential current path, and
A reference element (20) connected in a second branch (55) of the differential current path,
the comparator (3)
- A first inverter (11) having an input (14) and an output (15) and between a supply terminal (12) of the first inverter (11) and the reference potential terminal (8) is connected, and
- a second inverter (21) having an input (24) connected to the output (15) of the first inverter (11) and an output (25) connected to the input (14) of the first inverter (11 ) and between a supply terminal (22) of the second inverter (22) and ...

Description

The The present invention relates to a circuit arrangement with a non-volatile Memory cell, a use of the circuit arrangement and a method for operating a non-volatile memory cell.

Non-volatile memory cells are common elements to data such as serial numbers, trim settings of analog circuits or a number of a semiconductor body permanently in a semiconductor body save.

The documents US 4,730,129 . US 5,404,049 . US 5,418,487 . US 5,731,733 . US 6,091,273 . US 6,384,664 B1 and US 6,819,144 B2 describe circuit arrangements for operating non-volatile memory cells, designed as a fuse, English Fuse.

The documents US Pat. No. 6,421,293 B1 and US 6,525,955 B1 show once programmable memory cells in which a parameter of an insulator is changed during programming, and associated circuitry.

The document US 2005/0212086 A1 describes an antifuse which is designed as a Zener diode and which has a low resistance value in the programmed state and a high resistance value in the non-programmed state.

The documents "Lifetime Study for a Polyfuse in a 0.35 μm Polycide CMOS Process", J. Fellner, P. Bösmuller, H. Reiter, 43rd Annual IEEE International Reliability Physics Symposium, 17.-21. April 2005, Proceedings, pp. 446-449, and "A One Time Programming Cell Using More Resistance Levels of a PolyFuse," J. Fellner, 27th Annual IEEE Custom Integrated Circuits Conference, 18-21. September 2005, Proceedings, pages 263-266 as well US 5,976,943 deal with programmable resistors that span two layers. The layer deposited first on the semiconductor body comprises polysilicon and the second layer deposited on the semiconductor body comprises a silicide.

document US 2002/0008544 A1 relates to a circuit having a first and a second fuse element and a first and a second inverter. An output of the first inverter is connected to an input of the second inverter and an output of the second inverter is connected to an input of the first inverter. The first fuse element connects a supply terminal to the first inverter and the second fuse element connects the supply terminal to the second inverter.

task The present invention is a circuit arrangement with a non-volatile memory cell and to provide a method of operating a non-volatile memory cell, the an accurate evaluation of the programming state of the non-volatile Memory cell and a realization of the circuit arrangement with ensure a low cost of components.

These The object is with the subject of claim 1 and the Process according to claim 14 solved. Further developments and refinements are each the subject of dependent Claims.

According to the invention a circuit arrangement a non-volatile Memory cell, a reference element and a comparator. A differential Rung connects one supply voltage terminal to one Reference potential terminal. The comparator is symmetrical and switched to the differential rung. The comparator points a self-holding function. The non-volatile memory cell is in switched to a first branch of the differential current path and the reference element is in a second branch of the differential Rungs switched.

by virtue of the different resistance values of the reference element and the non-volatile Memory cell flow different currents in the first and in the second branch of the differential current path. By means of the comparator the different current flow in the first branch and in the second branch determined. Due to the self-holding function the comparator is an output signal obtained in this way on the output side provided at the comparator. The output signal is thus dependent on from the resistance of the non-volatile Memory cell and generated by the resistance value of the reference element.

It is an advantage of the circuit arrangement that due to the integration the comparator function and the self-holding function in one block a circuit complexity can be kept low. With Advantage is by means of the comparator and the reference element of the Programming state of non-volatile Memory cell accurately evaluable.

The comparator with self-hold function comprises a first and a second inverter. The first inverter couples a supply terminal of the first inverter to a reference potential terminal. Accordingly, the second inverter couples a supply terminal of the second inverter to the reference potential terminal. The first inverter and the second inverter each have an input and an exit on. The input of the second inverter is connected to the output of the first inverter and the output of the second inverter is connected to the input of the first inverter. Due to the different currents in the two branches of the differential current path, the two branches load up at different speeds. This difference is evaluated by the balanced comparator with a digital output signal. The feedback of the two inverters ensures the self-holding function of the output signal of the comparator.

The Circuit arrangement comprises a writing arrangement with a first Switch having a first input of the write array with the output of the first inverter, and a second switch, the one second input of the write arrangement with the output of the second Inverters couples. Furthermore, the writing arrangement has a control input on, with a control terminal of the first switch and a Control terminal of the second switch is coupled.

In an embodiment couples the non-volatile Memory cell the supply voltage connection to the supply connection of the first inverter and the reference element the supply voltage terminal to the supply terminal of the second inverter couples. In a embodiment For example, the first inverter has a first and a second transistor as well as the second inverter also a first and a second transistor on.

In In a further development, a first charging transistor couples the output of the first inverter to the reference potential terminal and couples a second charging transistor with the output of the second inverter with the reference potential connection. The first and the second charging transistor are connected to each other at a control terminal. Are the first and the second charging transistor turned on, are so the output of the first inverter and the output of the second Inverters at a low potential, approximately the reference potential. In a following step, the first and the second charging transistor simultaneously disabled, so load the non-volatile memory cell and the reference element the outputs of both inverters. Does the non-volatile memory cell have one higher Resistance value compared with the reference element increases a potential at the output of the second inverter faster as a potential at the output of the first inverter. Is the switching threshold reached the second inverter, so is at the output of the second inverter a high potential can be tapped. Due to the connection of the output of the second inverter with the input of the first inverter the first inverter is driven in such a way that it is at its output provides a low potential. The reverse is true in the case that the non-volatile Memory cell a lower resistance value compared to the Has reference element.

The nonvolatile Memory cell may be a mask-programmed memory cell. Alternatively, the non-volatile memory cell comprise a reversibly programmable memory cell. In another alternative embodiment can the non-volatile Memory cell realized as an irreversibly programmable memory cell be.

The nonvolatile Memory cell can be realized as a resistor, wherein a programming current the resistance value of the non-volatile Memory cell irreversibly enlarged. alternative can the non-volatile Memory cell be a fuse, English Fuse, by means of a Laser beam is programmed. The non-volatile memory cell is preferred as a fuse, English Fuse, realized by means of a Programming current includes fusible resistor. The non-volatile memory cell may be a metal resistor, a polysilicon resistor or a combined polysilicon / silicide resistance have.

In an alternative embodiment can the non-volatile memory cell be implemented as an antifuse element, wherein the resistance value irreversibly reducible by means of a programming current. In one embodiment the antifuse element can be used as a diode, in particular as a Zener diode, be realized.

The Reference element can be realized as a resistor, which has a resistance value which preferably between the resistance values of the non-volatile Memory cell before and after programming is.

The Circuitry may comprise a programming transistor between a terminal of the non-volatile memory cell and the reference potential terminal is switched. Another connection of the non-volatile Memory cell is connected to the supply voltage terminal. If the programming transistor is turned on, a high current flows Current through the non-volatile memory cell and sets a resistance value of the non-volatile memory cell, so the non-volatile Memory cell is programmed.

In an embodiment, the circuit arrangement comprises a compensation element which is connected to a terminal of the reference element and is coupled to the second branch of the differential current path. The compensation element is used to compensate for the capacitive load from the programming transistor in the first Branch of the differential current path is caused. Advantageously, by means of the compensation element a symmetrical capacitive load on the supply terminals of the first and the second inverter can be achieved. Advantageously, therefore, the capacitive and resistive loads in the first and second branches of the current path are approximately equal except for the resistance values of the non-volatile memory cell and the reference element.

The Circuit arrangement may be formed on a semiconductor body. The Circuitry can be implemented in a bipolar integration technique and transistors formed as bipolar transistors are. Preferably, it can by means of a complementary metal-oxide semiconductor Integration technology and have transistors, which are realized as field effect transistors.

The Circuitry can lead to a permanent storage of data be used. The data can a serial number or an identification number for the semiconductor body. Alternatively, the circuitry may be used to store a trim adjustment an analog circuit, in particular an analog / digital or a Digital / analog converter, be provided. It can be used to repair a Random Access Memory, abbreviated RAM, by turning on redundant rows or columns instead serve broken lines or columns.

According to the invention sees a method of operating a non-volatile Memory cell following steps: A supply voltage is provided. An output signal and an inverted output signal become dependent of a resistance value of a non-volatile memory cell and of set and held a resistance value of a reference element. Here are the non-volatile Memory cell in a first branch and the reference element in one second branch of a differential rung. Of the differential current path flows through a comparator.

With Ensure an advantage the comparator and the reference element provide an accurate reading of the in the non-volatile Memory cell stored information.

The Method for operating a non-volatile memory cell comprises setting and holding an output signal having a value of 1 and an inverted output signal with a value 0 in the case, that a non-volatile Memory cell a higher Has resistance value as a reference element, and adjusting and holding the output signal with a value of 0 and the inverted one Output signal with a value of 1 in the case that the non-volatile memory cell has a lower resistance than the reference element. there become the non-volatile Memory cell and a first branch of the differential current path a comparator of a first current and the reference element and a second branch of the differential current path of one second current flows through. The output signal and the inverted output signal be overwriting the output signal with a setting signal and the inverted Output signal adjusted with an inverted setting signal.

The Invention will be described below in several embodiments with reference to the Figures closer explained. Function or effect same components carry the same Reference numerals. Insofar as circuit parts or components in Their description does not correspond to their function the following figures repeated.

1 shows an exemplary embodiment of a circuit arrangement with a non-volatile memory cell according to the proposed principle,

2 shows an exemplary development of the circuit arrangement with a non-volatile memory cell according to the proposed principle,

3A to 3C show an exemplary embodiment of a non-volatile memory cell, which is designed as a fuse, and

4 shows an exemplary embodiment of a non-volatile memory cell, which is realized as an antifuse.

1 shows an exemplary embodiment of a circuit arrangement with a non-volatile memory cell 10 according to the proposed principle. The circuit arrangement has a first branch 35 and a second branch 55 on that between a supply voltage connection 9 and a reference potential connection 8th are switched. The first and second branches together form a differential current path of a comparator 3 , The comparator 3 has a first inverter 11 and a second inverter 21 on. The first inverter 11 is between a supply connection 12 of the first inverter 12 and the reference potential connection 8th connected and has a first transistor 30 and a second transistor 40 on, which are connected to each other in series. The transistors 30 . 40 are input side with an input 14 of the first inverter 11 connected. A tap between the first and the second transistor 30 . 40 of the first inverter 11 makes an exit 15 of the first inverter 11 , Accordingly, points the second inverter 21 a first transistor 50 and a second transistor 60 on that between a supply connection 22 of the second inverter 21 and the reference potential connection 8th are switched. The two transistors 50 . 60 of the second inverter 21 are input side to an input 24 of the second inverter 21 connected. A node between the first and the second transistor 50 . 60 of the second inverter 21 serves as an exit 25 of the second inverter 21 , The exit 15 of the first inverter 11 is with the entrance 24 of the second inverter 21 and the exit 25 of the second inverter 21 is with the entrance 14 of the first inverter 11 connected. The exit 15 of the first inverter 11 is via a first charging transistor 70 and the exit 25 of the second inverter 21 is via a second charging transistor 80 with the reference potential connection 8th coupled. The first and the second charging transistor 70 . 80 are connected on the input side.

At the supply voltage connection 9 a supply voltage VDD is connected. The control terminals of the first and the second charging transistor 70 . 80 a load signal LOAD can be fed. The first and the second charging transistor 70 . 80 are turned on in a first operating state.

Thus, the first transistor 30 and the first transistor 50 the first and the second inverter 11 . 21 conducting and the second transistor 40 and the second transistor 60 the first and the second inverter 11 . 21 switched off. In the two branches of the differential current path occur due to the different resistances of the non-volatile memory cell 10 and the reference element 20 different sized currents I1, I2 on the supply terminals 12 and 22 cause different voltage potentials. Be the two charging transistors 70 and 80 switched off, the comparator detects 3 the voltage difference between the supply connections 12 and 22 and stores the result latched in the two inverters 11 and 21 from.

Indicates the non-volatile memory cell 10 a smaller resistance than the reference element 20 On, the inverted output voltage NVOUT rises faster than the output voltage VOUT, so that due to the feedback of the first and the second inverter 11 . 21 the second transistor 60 of the second inverter 21 as well as the first transistor 30 of the first inverter 11 conductive and the two other transistors 50 . 40 are switched as a lock. At the exit 15 of the first inverter 11 is an inverse output signal NVOUT and at the output 25 of the second inverter 21 an output signal VOUT can be tapped off.

Advantageously, thus with a few components, a state of the non-volatile memory cell 10 detected and the output signal VOUT are held.

2 shows an exemplary development of in 1 shown embodiment of a circuit arrangement with a non-volatile memory cell. In addition to the circuit arrangement according to 1 has the circuit arrangement in 2 a programming transistor 150 on, the supply connection 12 of the first inverter 11 with the reference potential connection 8th combines. In addition, a compensation element 160 to the supply connection 22 of the second inverter 21 connected. The compensation element 160 is designed as a transistor.

At the exit 15 of the first inverter 11 is a first buffer 135 and to the exit 25 of the second inverter 21 is a second buffer 115 connected. The first buffer 135 comprises an inverter comprising a first and a second transistor 140 . 130 , on, between the supply voltage connection 9 and the reference potential connection 8th is switched. Accordingly, the second buffer 115 an inverter comprising a transistor 120 and a transistor 110 , on, between the reference potential terminal 8th and the supply voltage connection 9 is switched. The inputs of the two transistors 130 . 140 of the first buffer 135 are with the exit 15 of the first inverter 11 as well as the inputs of the transistors 120 . 110 of the second buffer 115 with the exit 25 of the second inverter 21 connected.

The exit 15 of the first inverter 11 is a first switch 100 a writing arrangement 89 upstream. Likewise, the exit 25 of the second inverter 21 a second switch 90 the writing arrangement 89 upstream. The control terminals of the first and second switches 90 . 100 are with each other and with a control input 92 the writing arrangement 89 connected.

The transistors 30 . 40 . 50 . 60 . 70 . 80 . 110 . 120 . 130 . 140 . 150 . 160 and the switches 90 . 100 can be realized as field effect transistors, in particular as metal oxide semiconductor field effect transistors, abbreviated MOSFETs.

The programming transistor 150 serves to provide a first current I1 with a high current value passing through the non-volatile memory cell 10 to perform a programming operation. Due to its size, the programming transistor 150 a capacitive load on the supply terminal 12 In the read process described above, the two branches 35 . 55 of the differential current path with advantage in equally loaded capacitively to a symmetrical design of the comparator 3 to ensure. This is the supply connection 22 of the second inverter 21 with the compensation element 160 connected. This compensation element 160 is designed as a transistor, and provides for the second branch 55 of the differential current path is the same capacitive loading as the programming transistor 150 for the first branch 35 of the differential current path.

Advantage is on the two outputs 15 . 25 the first and the second inverter 11 . 21 one buffer each 115 . 135 downstream, leaving a capacitive load at the output 15 of the first inverter 11 and a capacitive load at the output 25 of the second inverter 21 are approximately the same and not of in 2 not shown circuits, the output side of the first and the second inverter 11 . 21 can be changed, can be changed. Thus, downstream circuits do not affect the setting and switching operation of the first and second inverters 11 . 21 ,

Advantageously, by means of the writing arrangement 89 the output signal VOUT having the value of a setting signal DATAIN and the inverted output signal NVOUT having the value of the inverted setting signal NDATAIN are provided, as soon as by means of a write control signal WRITE the two switches 90 . 100 are switched on. Advantageously, it is therefore possible to data in a second manner in the two inverters 11 and 21 save, provided the non-volatile memory cell 10 is low impedance. This allows for test purposes data independent of the non-volatile memory cell 10 get saved.

Is the non-volatile memory cell 10 programmable by means of a laser beam, so in an alternative embodiment the programming transistor 150 and the compensation element 160 omitted.

In an alternative embodiment, a programming terminal shown in dashed lines 170 instead of the programming transistor 150 with the supply connection 12 of the first inverter 11 be connected. The programming connector 170 can be designed as externally contactable connection, English pad. If a voltage below the supply voltage VDD to the programming port 170 applied, the first current I1 can flow with a high value. By this current I1 is a programming of the non-volatile memory cell 10 possible.

3A to 3C show an exemplary embodiment of a non-volatile memory cell 10 which is designed as a backup. The non-volatile memory cell 10 is realized as Polyfuse.

3A shows an exemplary view of the non-volatile memory cell 10 , This includes a middle area 200 and a first and a second port 201 . 202 that go beyond the middle range 200 connected to each other. The first and the second connection 201 . 202 each have several contacts 203 on.

3B shows a cross section of the non-volatile memory cell 10 whose location in 3A is drawn. The non-volatile memory cell 10 is on an insulator layer 205 , which in turn on a carrier 204 realized is arranged. The middle area 200 has a double layer of a polysilicon layer 206 and a silicide layer 207 on. The polysilicon layer 206 is on the insulator 205 and the silicide layer 207 on the polysilicon layer 206 deposited. The contacts 203 are with the silicide layer 207 connected. In 3B is the non-volatile memory cell 10 shown before the programming process.

3C shows the non-volatile memory cell 10 after a programming operation with a sufficiently large value of the programming current. After the programming process is the silicide material 207 especially at the first connection 201 arranged. The original polysilicon layer 206 and the silicide layer 207 have segregated. The remainder forms a polymorphic silicon layer 208 that deals with the insulator 205 and the insulator layer 209 has mixed. The non-volatile memory cell 10 according to 3C has a resistance in the megohm range.

4 shows another exemplary embodiment of a non-volatile memory cell 10 , which is designed as an antifuse and comprises a diode. The diode is realized as a Zener diode. 4A shows the non-volatile memory cell 10 in supervision. This has oppositely doped areas 302 . 303 on, showing a lateral pn junction in a contact area 300 form. The area 302 is n-doped; The area 303 is p-doped. In the two doped areas 302 . 303 are connections 304 . 305 arranged. The non-volatile memory cell 10 is programmable by means of a first current I1. Prior to programming, the diode has a high resistance value and a comparatively low leakage current and, after programming, a low resistance value and a high current flow. In the programmed state, the diode can approximate a behavior like a resistor.

3

comparator

8th

Reference potential terminal

9

supply terminal

10

non-volatile memory cell

11

first inverter

12

supply terminal

14

entrance

15

output

20

reference element

21

second inverter

22

supply terminal

24

entrance

25

output

30

first transistor

35

first branch

40

second transistor

50

first transistor

55

second branch

60

second transistor

70

first charging transistor

80

second charging transistor

89

write assembly

90

second switch

91

second entrance

92

control input

100

first switch

101

first entrance

110

transistor

115

second buffer

120

transistor

130

transistor

135

first buffer

140

transistor

150

programming transistor

160

compensation element

170

programming port

200

middle Area

201 202

connection

203

Contact

204

carrier

205

insulator

206

Polysilicon layer

207

Silicide layer

208

polymorphous silicon layer

209

insulator layer

300

Contact area

302

n-doped area

303

p-doped area

304 305

connections

BURN

programming signal

DATAIN

adjustment

DATAOUT

buffered output voltage

I1

first electricity

I2

second electricity

LOAD

load signal

VOUT

output voltage

VDD

supply voltage

VSS

reference potential

NDATAIN

inverted adjustment

NDATAOUT

buffered, inverted output voltage

NVout

inverted output voltage

WRITE

Write control signal

Claims (17)

Circuit arrangement with a non-volatile memory cell, comprising - a symmetrically constructed comparator ( 3 ) comprising a self-holding function and a differential current path connecting a supply voltage terminal ( 9 ) with a reference potential connection ( 8th ), is connected, - the non-volatile memory cell ( 10 ) in a first branch ( 35 ) of the differential current path, and - a reference element ( 20 ), which is in a second branch ( 55 ) of the differential current path, the comparator ( 3 ) - a first inverter ( 11 ), which has an entrance ( 14 ) and an output ( 15 ) and between a supply connection ( 12 ) of the first inverter ( 11 ) and the reference potential terminal ( 8th ), and - a second inverter ( 21 ), which has an entrance ( 24 ) connected to the output ( 15 ) of the first inverter ( 11 ) and an output ( 25 ), with the entrance ( 14 ) of the first inverter ( 11 ) and between a supply connection ( 22 ) of the second inverter ( 22 ) and the reference potential terminal ( 8th ), and the circuit arrangement comprises a write arrangement ( 89 ) with - a first switch ( 100 ), which has a first entrance ( 101 ) the writing arrangement ( 89 ) with the output ( 15 ) of the first inverter ( 11 ), - a second switch ( 90 ), which has a second input ( 91 ) the writing arrangement ( 89 ) with the output ( 25 ) of the second inverter ( 21 ), and - a control input ( 92 ) connected to a control terminal of the first switch ( 100 ) and a control terminal of the second switch ( 90 ). Circuit arrangement according to claim 1, characterized in that - the non-volatile memory cell ( 10 ) between the supply connection ( 12 ) of the first inverter ( 11 ) and the supply voltage connection ( 9 ) and - the reference element ( 20 ) between the supply connection ( 22 ) of the second inverter ( 21 ) and the supply voltage connection ( 9 ) is. Circuit arrangement according to Claim 1 or 2, characterized in that the first inverter ( 11 ) - a first transistor ( 40 ), which - at a first connection to the reference potential connection ( 8th ) and - at a control connection with the input ( 14 ) of the first inverter ( 11 ), and - a second transistor ( 30 ), which - at a first connection to the supply connection ( 12 ) of the first inverter ( 11 ), - at a control connection with the input ( 14 ) of the first inverter ( 11 ) and - at a second terminal to a second terminal of the first transistor ( 40 ) of the first inverter ( 11 ) and with the output ( 15 ) of the first inverter ( 11 ). Circuit arrangement according to one of claims 1 to 3, characterized in that the second inverter ( 21 ) - a first transistor ( 60 ), which - at a first connection to the reference potential connection ( 8th ) and - at a control connection with the input ( 24 ) of the second inverter ( 21 ), and - a second transistor ( 50 ), which - at a first connection to the supply connection ( 22 ) of the second inverter ( 21 ), - at a control connection with the input ( 24 ) of the second inverter ( 21 ) and - at a second terminal to a second terminal of the first transistor ( 60 ) of the second inverter ( 21 ) and with the output ( 25 ) of the second inverter ( 21 ). Circuit arrangement according to one of claims 1 to 4, characterized in that the circuit arrangement - a first charging transistor ( 70 ) between the output ( 15 ) of the first inverter ( 11 ) and the reference potential connection ( 8th ), and - a second charging transistor ( 80 ) between the output ( 25 ) of the second inverter ( 21 ) and the reference potential connection ( 8th ) and having a control terminal connected to a control terminal of the first charging transistor ( 70 ). Circuit arrangement according to one of claims 1 to 5, characterized in that the circuit arrangement - a first buffer ( 135 ), the output ( 15 ) of the first inverter ( 11 ), and - a second buffer ( 115 ), the output ( 25 ) of the second inverter ( 21 ) downstream. Circuit arrangement according to one of Claims 1 to 6, characterized in that the non-volatile memory cell ( 10 ) is designed as an irreversibly programmable memory cell. Circuit arrangement according to one of Claims 1 to 7, characterized in that the non-volatile memory cell ( 10 ) is designed as a resistor whose resistance value can be irreversibly increased by means of a programming current. Circuit arrangement according to one of Claims 1 to 8, characterized in that the non-volatile memory cell ( 10 ) is designed as a fuse, which can be fused by means of a programming current. Circuit arrangement according to one of Claims 1 to 7, characterized in that the non-volatile memory cell ( 10 ) is designed as an antifuse whose resistance value is irreversibly reduced by means of a programming current. Circuit arrangement according to one of claims 1 to 10, characterized in that the reference element ( 20 ) is designed as a resistor. Circuit arrangement according to one of claims 1 to 11, characterized in that the circuit arrangement - a programming transistor ( 150 ), one terminal of the non-volatile memory cell ( 10 ) with the reference potential connection ( 8th ), and - a compensation element ( 160 ) connected to a terminal of the reference element ( 20 ) is connected to the node ( 12 . 22 ) to achieve symmetric capacitive loading includes. Use of the circuit arrangement according to one of claims 1 to 12 for the permanent storage of data, in particular one Serial number, a semiconductor body number or a trim adjustment of an analog circuit on a semiconductor body, the the circuit comprises. Method for operating a non-volatile memory cell, comprising the following steps: - providing a supply voltage (VDD), - setting and holding an output signal (VOUT) with a value 1 and an inverted output signal (NVOUT) with a value 0 in the case where a non-volatile memory cell ( 10 ) has a higher resistance than a reference element ( 20 ) and setting and holding the output signal (VOUT) with a value of 0 and the inverted output signal (NVOUT) with a value of 1 in the case that the non-volatile memory cell ( 10 ) has a lower resistance than the reference element ( 20 ), wherein the non-volatile memory cell ( 10 ) and a first branch ( 35 ) of the differential current path of a comparator ( 3 ) of a first current (I1) and the reference element ( 20 ) and a second branch ( 55 a second current (I2) flows through the differential current path, - adjusting the output signal (VOUT) and the inverted output signal (NVOUT) by overwriting the output signal (VOUT) with an adjustment signal (DATAIN) and the inverted output signal (NVOUT) with a inverted setting signal (NDATAIN). A method according to claim 14, characterized by providing a load signal (LOAD) having a first value for lowering the output signal (VOUT) and the inverted output signal (NVOUT), providing the load signal (LOAD) with a second value different from the first one Value, to charge a first output ( 25 ) of the comparator ( 3 ) and as a result increase of the output signal (VOUT) in dependence on the reference element ( 20 ) and charging a second output ( 15 ) of the comparator ( 3 ) and as a result increase the inverted output signal (NVOUT) in dependence on the non-volatile memory cell ( 10 ), - Comparing the output signal (VOUT) with the inverted output signal (NVOUT), providing the output signal (VOUT) and the inverted output signal (NVOUT) in dependence on a comparison result. A method according to claim 14 or 15, characterized by separately buffering the output signal (VOUT) and the inverted one Output signal (NVOUT). Method according to one of Claims 14 to 16, characterized by programming the non-volatile memory cell ( 10 ) by driving a programming transistor ( 150 ) with a programming signal (BURN) in such a way that a programming current generated by the supply voltage (VDD) is transmitted via the non-volatile memory cell (10). 10 ) and the programming transistor connected in series ( 150 ) flows.