JPH1197553A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance or high-functional semiconductor device which can greatly reduce the number of manufacturing steps in a CMOS transistor and can be manufactured with a low price. SOLUTION: A MOS transistor formed on a semiconductor substrate is surrounded by groove/element isolation areas 5, 10, sides of a gate electrode pattern of the MOS transistor in its channel direction are formed as self-aligned, an insulating film is buried in the groove/element isolation areas 5, 10, and a side wall insulating film is formed which is made of the same material as the first insulating film is formed on side walls of gate electrodes 3, 8. Or a low-concentration diffusion layer to be later formed as a source/drain region of an LDD structure of a CMOS transistor as well as a channel stop region at the bottom of the groove/element isolation region are simultaneously formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an LDD (Lightly Doped).
(Drain) structure.

[0002]

2. Description of the Related Art A conventional method for forming a channel stopper region formed in an element isolation region of a CMOS transistor and a diffusion layer of a CMOS transistor having an LDD structure will be described with reference to FIGS. Figure 4 shows such a CM
FIG. 3 is a plan view schematically illustrating an OS transistor. 5 and 6 are cross-sectional views in the order of manufacturing steps in the case of the conventional technique. Here, the section taken along the line CD shown in FIG. 4 is the cross section of FIG. 5 and FIG.

As shown in FIG. 4, an N-well 102 is formed on a silicon substrate 101 having a P-type conductivity. Then, P is formed on the silicon substrate 101 via a gate oxide film.
A gate electrode 103 of the channel MOS transistor is formed. Further, source / drain diffusion layers 104 are formed with the gate electrode 103 interposed therebetween. here,
The width of the source / drain diffusion layer 104, that is, the channel width of the MOS transistor is formed to be shorter than the pattern length of the gate electrode 103. Then, an N-well extraction diffusion layer 105 is formed in a predetermined region of the N-well 102.
Is formed. As described above, P-channel MOS transistor 106 is formed.

A gate electrode 107 of an N-channel MOS transistor is formed on a silicon substrate 101 via a gate oxide film. Further, source / drain diffusion layers 108 are formed with the gate electrode 107 interposed therebetween. Here, the width of the source / drain diffusion layer 108 is formed to be shorter than the pattern length of the gate electrode 107. Then, a substrate lead diffusion layer 109 is formed in a predetermined region of the silicon substrate 101. In this way,
An N-channel MOS transistor 110 is formed.

Next, a method of manufacturing the above-described CMOS transistor will be described with reference to FIGS. FIG.
(A) As shown in FIG.
An N-well 102 is formed in a predetermined region on the N.I. Then, a mask oxide film 111 and a resist mask 112 are formed on the silicon substrate 101, and the surface of the silicon substrate 101 is subjected to reactive ion etching (RI
The groove 114 is formed by dry etching in E). After that, the resist mask 112 is removed.

Next, as shown in FIG. 5B, a resist mask 115 is formed by a known photolithography technique. Then, an N-type impurity such as phosphorus is ion-implanted using the resist mask 115 as a mask, and an N-type implanted layer 116 is formed in a predetermined region of the groove 114 in the N well 102. After that, the resist mask 115 is removed.

Next, as shown in FIG. 5C, a resist mask 117 is formed again by photolithography. Then, a P-type impurity such as boron is ion-implanted using the resist mask 117 as a mask, and a P-type implanted layer 118 is formed in a predetermined region of the groove 114. After that, the resist mask 115 is removed.

Next, a silicon oxide film is deposited on the entire surface by a chemical vapor deposition (CVD) method, and is subjected to chemical mechanical polishing (CMP). As shown in FIG. The oxide film 119 is filled. Then, the mask oxide film 111 is removed, and the gate oxide film 1 is formed by a thermal oxidation method.
20 are formed. Further, gate electrodes 103 and 107 of a P-channel MOS transistor and an N-channel MOS transistor are formed on gate oxide film 120.

Then, a heat treatment is performed.
An N-type channel stopper region 121 is formed in the mold injection layer 116, and a P-type channel stopper region 122 is formed in the P-type implantation layer 118. Next, a source / drain P-type implantation layer 1 is formed in a region where a P-channel MOS transistor is formed by ion implantation of boron impurities.
23 are formed. Then, source / drain N-type implanted layers 124 are formed in the regions where the N-channel MOS transistors are formed by ion implantation of N-type impurities such as phosphorus.

Next, heat treatment is performed. By this heat treatment, as shown in FIG. 6B, a low-concentration P-type diffusion layer 125 is formed in the source / drain P-type injection layer 123. Then, similarly, a low-concentration N-type diffusion layer 126 is formed in the source / drain N-type injection layer 124.

Next, a silicon oxide film is deposited on the entire surface by the CVD method, etched back by RIE, and a side wall insulating film 127 is formed on the side walls of the gate electrodes 103 and 107.

After the side wall insulating film is formed on the side wall of the gate electrode of the MOS transistor in this manner, ion implantation of BF ₂ or the like and heat treatment are performed, as shown in FIG.
As shown in FIG. 7, a high-concentration P-type diffusion layer 128 is formed in the low-concentration P-type diffusion layer 125 region. In this manner, the source / drain diffusion layers 104 of the P-channel MOS transistor described with reference to FIG. 4 are formed. Similarly, by ion implantation of arsenic or the like and heat treatment, the high concentration N-type diffusion layer 12 is formed in the low concentration N-type diffusion layer 126 as shown in FIG.
9 is formed. Then, the N channel M described in FIG.
The source / drain diffusion layer 108 of the OS transistor is formed. Such source / drain diffusion layers 104 and 108 have an LDD structure.

Next, as shown in FIG. 6C, an interlayer insulating film 130 is formed, and a contact hole 131 is formed in a predetermined region of the interlayer insulating film 130. Although the subsequent steps are not shown, a wiring layer is formed by a known method to complete the MOS transistor.

[0014]

The above-described method is a conventional method for manufacturing a CMOS transistor. Semiconductor devices composed of such CMOS transistors are becoming more highly integrated and faster. Further, a semiconductor device in which, for example, a logic circuit and a memory circuit are mounted on the same semiconductor chip has been developed, which is called system-on-silicon.

As described above, when the semiconductor device has high performance or high function, the manufacturing process of the semiconductor device is generally lengthened and the manufacturing cost is increased. Then, the semiconductor device becomes expensive, and the application of the semiconductor device having high performance or high function to equipment is hindered.

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can significantly reduce the number of manufacturing steps of a CMOS transistor and can solve the above-mentioned problems in the conventional technology.

[0017]

For this purpose, in the semiconductor device of the present invention, a MOS transistor formed on a semiconductor substrate is surrounded by a trench element isolation region, and a side of a gate electrode pattern of the MOS transistor in a channel direction is formed. An insulating film is formed in a self-aligned manner with respect to the trench element isolation region, an insulating film is buried in the trench element isolation region, and an insulating film of the same material as the insulating film is formed on a side wall of the gate electrode.

The method of manufacturing a semiconductor device described above includes:
Forming a gate oxide film and a conductive film on a semiconductor substrate by lamination, and then processing the conductive film once into a first pattern; and forming the first pattern of the conductive film in the channel direction. Processing a side and the surface of the semiconductor substrate into a predetermined shape to form the conductive film in the second pattern to form the gate electrode and simultaneously form a groove in the surface of the semiconductor substrate; Depositing and etching back to bury the insulating film in the trench and simultaneously forming a sidewall insulating film with the insulating film on a side wall of the gate electrode.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, in a step of forming a CMOS transistor on a semiconductor substrate, an LD constituting the CMOS transistor may be used.
D-channel N-channel MOS transistor and P-channel M
Forming trenches so as to surround the respective OS transistors;
A lightly doped N-type diffusion layer serving as a source / drain region of the structure and a channel stopper region at the bottom of the trench surrounding the P-channel MOS transistor are simultaneously formed, and the source / drain of the LDD structure of the P-channel MOS transistor is formed.
Simultaneously forming a low-concentration P-type diffusion layer serving as a drain region and a channel stopper region at the bottom of the trench surrounding the N-channel MOS transistor.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, in the step of forming a CMOS transistor on a semiconductor substrate, grooves are formed so as to surround the N-channel MOS transistor and the P-channel MOS transistor constituting the CMOS transistor, respectively. Forming and depositing an insulating film on the entire surface and performing an etch back to bury the insulating film in the trench, and simultaneously forming a sidewall insulating film on a sidewall of a gate electrode of the CMOS transistor.

Alternatively, after forming the low-concentration N-type diffusion layer, the low-concentration P-type diffusion layer and the channel stopper region in the source / drain regions of the LDD structure, an insulating film is deposited on the entire surface and etched back. At the same time as filling the trench with the insulating film, a sidewall insulating film is formed on a side wall of the gate electrode of the CMOS transistor.

[0022]

Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows C of the present invention.
FIG. 2 is a schematic plan view of a MOS transistor. And
2 and 3 are cross-sectional views of a CMOS transistor according to the present invention in the order of manufacturing steps. Here, the section taken along the line AB shown in FIG. 1 is a cross section of FIG. 2 and FIG.

As shown in FIG. 1, an N well 2 is formed in a predetermined region on a silicon substrate 1 having a P type conductivity.
A gate electrode 3 of a P-channel MOS transistor is formed on silicon substrate 1 with a gate oxide film interposed therebetween.

Further, with the gate electrode 3 interposed, the source
A drain diffusion layer 4 is formed. And the source
A trench element isolation region 5 is formed so as to completely surround the drain diffusion layer 4 and the gate electrode 3. Here, the width of the source / drain diffusion layer 4, that is, the channel width of the MOS transistor is formed to be the same as the pattern length of the gate electrode 3. That is, the sides of the gate electrode 3 pattern in the channel direction are formed so as to be self-aligned (self-aligned) with the trench element isolation region 5. Then, an N-well lead diffusion layer 6 is formed in a predetermined region of the N-well 2. As described above, the P-channel MOS transistor 7 is formed.

A gate electrode 8 of an N-channel MOS transistor is formed on silicon substrate 1 with a gate oxide film interposed therebetween. Further, source / drain diffusion layers 9 are formed with the gate electrode 8 interposed therebetween. Then, a trench element isolation region 10 is formed so as to completely surround the source / drain diffusion layer 9 and the gate electrode 8. here,
The width of the source / drain diffusion layer 9, that is, the channel width of the MOS transistor is formed to be the same as the pattern length of the gate electrode 8. Also in this case, the side of the gate electrode 8 pattern in the channel direction is the groove element isolation region 10
Is formed so as to be self-aligned with respect to.
Then, a substrate leading diffusion layer 11 is formed in a predetermined region of the silicon substrate 1. As described above, the P-channel MOS transistor 12 is formed.

Next, referring to FIGS. 2 and 3, the CM of the present invention will be described.
A method for manufacturing an OS transistor will be described. As shown in FIG. 2A, an N well 2 is formed in a predetermined region on a silicon substrate 1 having a P type conductivity. Then, a gate oxide film 13 is formed on the silicon substrate 1 by a thermal oxidation method. Then, the conductor film is dry-etched by RIE using the resist mask 14, and the gate electrodes 3 and 8 are formed. Here, a polycrystalline silicon film containing a phosphorus impurity, a tungsten polycide film, or the like is used as the conductor film.

Then, as shown in FIG. 2B, a new resist mask 15 is formed by a known photolithography technique, and the surface of the silicon
The groove 16 is formed by dry etching with E. Here, the width and depth of the groove 16 are set to be about 0.5 μm. After that, the resist mask 15 is removed. By this dry etching, the sides of the gate electrodes 3 and 8 in the channel direction are simultaneously processed, and the gate electrodes are formed so as to be self-aligned with the grooves.

Next, as shown in FIG. 2C, a resist mask 17 is formed by a known photolithography technique. Then, using the resist mask 17 as a mask for ion implantation, phosphorus impurities are ion-implanted. Here, the implantation energy of the phosphorus impurity is 70 keV, and the dose is 1 × 10 ¹³ / cm ² . By this ion implantation, the bottom of the groove 16 in the N well 2 and the N
An N-type injection layer 18 is formed in a region to be a source / drain diffusion layer of the channel MOS transistor. Then, the resist mask 17 is removed.

Next, as shown in FIG. 2D, a resist mask 19 is formed again by photolithography. Then, boron impurities are ion-implanted using the resist mask 19 as a mask. Here, the implantation energy of the boron impurity is 30 keV, and the dose amount is 1 ×.
10 ¹³ / cm ² . By this ion implantation, the source of the P-channel MOS transistor and the bottom of the groove 16 in the region where the N-channel MOS transistor is formed are simultaneously formed.
A P-type injection layer 20 is formed in a region to be a drain diffusion layer. Then, the resist mask 19 is removed. Then, a heat treatment is performed.

In this manner, as shown in FIG. 3A, an N-type channel stopper region 21 is formed at the bottom of the groove in the N well 2. At the same time, a low-concentration P-type diffusion layer 22 is formed on the surface of the N well 2. In the region where the N-channel MOS transistor is formed, a P-type channel stopper region 23 and a low-concentration N-type diffusion layer 24 are formed.

Next, an oxide film 25 is deposited on the entire surface by the CVD method, and the trench 16 is filled with the oxide film 25. Here, the oxide film 25 is a silicon oxide film having a thickness of 400 nm.

Next, the entire surface of the oxide film 25 is etched back by RIE. With this etch back,
As shown in FIG. 3B, an element isolation oxide film 26 is formed in the groove 16.
Will be filled. At the same time, the sidewall insulating films 27 are formed on the side walls of the gate electrodes 3 and 8.

Next, a high-concentration P-type diffusion layer 28 is formed in the low-concentration P-type diffusion layer 22 region by ion implantation of boron or the like and heat treatment, as shown in FIG. In this manner, the source / drain diffusion layers 4 of the P-channel MOS transistor described with reference to FIG. 1 are formed. Similarly, by heat treatment with ions such as arsenic, the high-concentration N-type diffusion layer 2 is formed in the low-concentration N-type diffusion layer 24 as shown in FIG.
9 is formed. Then, the N-channel M described in FIG.
The source / drain diffusion layer 9 of the OS transistor is formed. Such a source / drain diffusion layer 4
And 9 become LDD structures.

Next, as shown in FIG. 3C, an interlayer insulating film 30 is formed, and a contact hole 31 is formed in a predetermined region of the interlayer insulating film. Although the subsequent steps are not shown, a wiring layer is formed by a known method to complete the MOS transistor.

As described above, a P-channel MOS transistor in which the element is isolated by the N-type channel stopper region 21 and the element isolation oxide film 26 and the sidewall insulating film 27 is formed on the side wall of the gate electrode 3 is formed. . At the same time, the P-type channel stopper region 23 and the device isolation oxide film 2
6, a P-channel MOS transistor having a sidewall insulating film 27 formed on the side wall of the gate electrode 8 is formed.

In the present invention, the element isolation oxide film 26 and the sidewall insulating film 27 filling the trench 16 are formed simultaneously in the same step. Further, the N-type channel stopper region 21 formed at the bottom of the groove 16 and the low-concentration N-type diffusion layer 2 are formed.
4 are formed simultaneously in the same step. Similarly, the P-type channel stopper region 23 and the low-concentration P-type diffusion layer 22 are simultaneously formed in the same step.

As described above, according to the present invention, the number of steps for manufacturing a CMOS transistor is greatly reduced. Then, the manufacturing cost of the semiconductor device is reduced, and a high-performance or high-performance semiconductor device can be realized at a low price.

[0038]

As described above, in the semiconductor device of the present invention, the MOS transistor formed on the semiconductor substrate is surrounded by the trench element isolation region, and the side in the channel direction of the gate electrode pattern of the MOS transistor is formed. An insulating film is formed in a self-aligned manner with respect to the trench element isolation region, an insulating film is buried in the trench element isolation region, and a sidewall insulating film is formed on the side wall of the gate electrode using an insulating film of the same material as the insulating film. Become so.

Alternatively, a CM formed on a semiconductor substrate
In the OS transistor, a trench is formed so as to surround the N-channel MOS transistor and the P-channel MOS transistor having the LDD structure constituting the CMOS transistor, respectively. An N-type diffusion layer and a channel stopper region at the bottom of the groove surrounding the P-channel MOS transistor are simultaneously formed, and a low-concentration P-type diffusion layer serving as a source / drain region of an LDD structure of the P-channel MOS transistor and the N-channel The channel stopper region at the bottom of the groove surrounding the MOS transistor is formed at the same time.

In this way, the number of manufacturing steps of the CMOS transistor is greatly reduced. Then, the manufacturing cost of the semiconductor device is reduced, and a high-performance or high-performance semiconductor device can be realized at a low price.

Then, the application of semiconductor devices such as system-on-silicon having high performance or high function to equipment will be promoted.

[Brief description of the drawings]

FIG. 1 is a plan view of a CMOS transistor illustrating an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a CMOS transistor in a manufacturing process order for describing the above-described embodiment;

FIG. 3 is a cross-sectional view illustrating a CMOS transistor in a manufacturing process order for describing the above-described embodiment;

FIG. 4 is a plan view of a CMOS transistor for explaining a conventional technique.

FIG. 5 is a cross-sectional view of a CMOS transistor for explaining a conventional technique in the order of manufacturing steps.

FIG. 6 is a cross-sectional view of a CMOS transistor for explaining a conventional technique in a manufacturing process order.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1,101 Silicon substrate 2,102 N well 3,8,103,107 Gate electrode 4,9,104,109 Source / drain diffusion layer 5,10 Trench element isolation region 6,106 N well lead diffusion layer 7,106 P Channel MOS transistors 11, 109 Substrate extraction diffusion layer 12, 110 N-channel MOS transistors 13, 120 Gate oxide film 14, 15, 17, 19, 112, 115, 117
Resist mask 16, 114 Groove 18, 116 N-type injection layer 20, 118 P-type injection layer 21, 121 N-type channel stopper region 22, 125 Low-concentration P-type diffusion layer 23, 122 P-type channel stopper region 24, 126 Low-concentration N type diffusion layer 25 Oxide film 26, 119 Element isolation oxide film 27, 127 Side wall insulation film 28, 128 High concentration P type diffusion layer 29, 129 High concentration N type diffusion layer 30, 130 Interlayer insulation film 31, 131 Contact hole 123 Source / drain P-type injection layer 124 Source / drain N-type injection layer

Claims (5)

[Claims] 1. An insulated gate field effect transistor formed on a semiconductor substrate is surrounded by a trench element isolation region, and a side of a gate electrode pattern of the insulated gate field effect transistor in a channel direction is positioned with respect to the trench element isolation region. A semiconductor device which is formed in a self-aligned manner, an insulating film is buried in the trench element isolation region, and an insulating film of the same material as the insulating film is formed on a side wall of the gate electrode. 2. A step of forming a gate oxide film and a conductor film on a semiconductor substrate and then processing the conductor film into a first pattern once, and forming a first pattern on the conductor film. Forming a groove on the surface of the semiconductor substrate at the same time as processing the side in the channel direction and the surface of the semiconductor substrate into a predetermined shape to form the conductive film in the second pattern as the gate electrode; Depositing an insulating film on the entire surface and performing an etch back to bury the insulating film in the trench, and simultaneously forming a sidewall insulating film with the insulating film on a side wall of the gate electrode. Item 1
The manufacturing method of the semiconductor device described in the above. 3. A method of forming a CMOS transistor on a semiconductor substrate, comprising the steps of:
Forming trenches so as to respectively surround the channel MOS transistors; and forming a low-concentration N region serving as a source / drain region of an LDD structure of the N-channel MOS transistors.
A low-concentration P-type diffusion layer which forms a P-type MOS transistor and a channel stopper region at the bottom of the trench surrounding the P-channel MOS transistor at the same time, and serves as a source / drain region of an LDD structure of the P-channel MOS transistor; Forming a channel stopper region at the bottom of the trench surrounding the MOS transistor at the same time. 4. A method of forming a CMOS transistor on a semiconductor substrate, comprising the steps of: forming an N-channel MOS transistor and a P-channel MOS transistor constituting the CMOS transistor;
Forming a groove so as to surround each of the S transistors; and depositing an insulating film on the entire surface and performing an etch back to bury the insulating film in the groove, and at the same time, a sidewall insulating film is formed on a side wall of a gate electrode of the CMOS transistor. Forming a semiconductor device. 5. After forming the low-concentration N-type diffusion layer, the low-concentration P-type diffusion layer and the channel stopper region in the source / drain regions of the LDD structure, an insulating film is deposited on the entire surface and etched back. 4. The method according to claim 3, wherein a sidewall insulating film is formed on a side wall of a gate electrode of the CMOS transistor at the same time as the insulating film is embedded in the trench.