JPH1188793A - Television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a television receiver capable of performing multi-screen display by a dynamic image and also reproducing a past video. SOLUTION: A tuner 2 is controlled so that plural channels are successively selected by a channel selection control part 3. Each of video signals of the plural channels obtained from the tuner 2 is successively compressed by high efficiency encoding, written in memory 7 and stored in the memory 7 at least by every field by a compression and writing processing circuit 11. The video signals stored in the memory 7 are read, extended and an interpolation or thinning processing of the video signals is simultaneously performed according to the number of the video to be displayed on a display part 10 by an extension and reading processing circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver for displaying all receivable channels or an arbitrary plurality of channels simultaneously on one screen.

[0002]

2. Description of the Related Art At present, various techniques such as picture-in-picture two-screen display have been proposed and commercialized as a multi-screen display method in a television receiver. As one of the television receivers, there is a television receiver which displays all receivable channels or an arbitrary plurality of channels simultaneously on one screen. In this case, the display image is generally a still image or a still image whose display content is updated at regular intervals.

FIG. 4 is a block diagram showing the configuration of this type of television receiver. In FIG. 4, the antenna 1
The signal based on the broadcast signal wave received at is detected by the tuner 2 and is converted by the IF circuit 4 into a composite video signal. Note that the tuner 2 is controlled by the channel selection control unit 3, and a predetermined channel is selected. The composite video signal output from the IF circuit 4 is Y / C
The signal is input to the separation / color demodulation circuit 5 and converted into a component video signal.

The component video signal output from the Y / C separation / color demodulation circuit 5 is subjected to an appropriate thinning process by a writing processing circuit 6 according to a display screen, and the memory 7
Is written to the specified memory space. The signals stored in the memory 7 are read by the read processing circuit 8 and subjected to interpolation processing as necessary. Then, luminance and color processing are performed by the signal processing circuit 9 and displayed on the display unit 10.

When performing multi-screen display, the tuning control unit 3
In this way, the tuner 2 performs channel selection sequentially over a plurality of channels, and writes a signal to a designated memory space of the memory 7 for each channel. And the display unit 1
A signal is read from the memory 7 according to the display mode at 0. Thereby, for example, as shown in FIG.
At 0, an image of 1 to 9 of 3 horizontal screens × 3 vertical screens can be displayed.

[0006]

However, since the video signal data has a huge amount of information, it takes a long time to write the data into the memory 7, and the multi-screen display on the display unit 10 is basically performed as described above. Has a problem that the still image is awkward. Further, since the capacity of the memory 7 is limited, there is a problem that the video signal must be overwritten for each field, and a missed scene cannot be replayed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a television receiver capable of performing multi-screen display with moving images and reproducing past images. I do.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention provides a tuner (2) for receiving a broadcast signal wave in a television receiver for displaying a plurality of images on a display unit. A tuning control unit (3) for controlling the tuner so as to sequentially tune all the channels receivable by the tuner or a plurality of channels among the channels, and images of the plurality of channels obtained from the tuner A compression / write processing circuit (11) for sequentially encoding and compressing the signals in units of at least one field, writing and storing the signals in a memory (7), and reading and expanding the video signals stored in the memory; Along with
It is an object of the present invention to provide a television receiver characterized by comprising a decompression / readout processing circuit (12) for performing interpolation or thinning-out processing according to the number of videos displayed on the display unit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a television receiver according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of a television receiver of the present invention, and FIGS. 2 and 3 are diagrams for explaining the operation of the television receiver of the present invention. In FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals.

In FIG. 1, a signal based on a broadcast signal wave received by an antenna 1 is detected by a tuner 2 and an IF
The circuit 4 converts the signal into a composite video signal.
The tuner 2 is controlled by the tuning control unit 3,
A predetermined channel is selected. The composite video signal output from the IF circuit 4 is input to a Y / C separation / color demodulation circuit 5 and converted into a component video signal.

The component video signal output from the Y / C separation / color demodulation circuit 5 is supplied to a compression / writing processing circuit 11.
And is written into the specified memory space of the memory 7. The compression / write processing circuit 11 stores at least one field (or one frame) for
The video signal is compressed by performing processing in the order of DCT transformation → quantization → entropy encoding by high-efficiency encoding such as PEG.

The video signal input to the compression / writing processing circuit 11 may be an R, B, or G signal, but it is necessary to convert the video signal into a Y, U, or V signal in order to obtain a large compression ratio. Is desirable. Note that the U and V signals are data relating to color, and large compression is possible due to the characteristic that human eyes are insensitive to color. DCT transformation is JPE
It is used for standard compression such as G and MPEG, and various other conversion methods such as wavelet conversion as non-standard compression can be used.

The signals stored in the memory 7 are read out by a decompression / readout processing circuit 12 and subjected to decompression processing. That is, the decompression / readout processing circuit 12 decompresses (restores) the video signal by performing processing completely opposite to the above-described compression, that is, processing in the order of entropy decoding → inverse quantization → inverse DCT transform. . When performing multi-screen display on the display unit 10, the decompression / readout processing circuit 12 performs interpolation processing or thinning processing after decompression processing. The output of the decompression / readout processing circuit 12 is input to the signal processing circuit 9, subjected to luminance and color processing, and displayed on the display unit 10.

When performing multi-screen display, the tuning control unit 3
In this way, the tuner 2 performs channel selection sequentially over a plurality of channels, and writes a signal to a designated memory space of the memory 7 for each channel. And the display unit 1
A signal is read from the memory 7 according to the display mode at 0.

The operation according to the present invention will now be described with reference to FIGS.
This will be further described with reference to FIG. As shown in FIG. 2, by selecting the tuner 2 sequentially over a plurality of channels by the tuning control unit 3, as shown in FIG. n, 1F, 2F, 3F as shown by the broken line for each field or frame.
... are sequentially output. After outputting nF of the video signal n, the process returns to the video signal 1 again and repeats.

Although illustration is omitted in FIG. 1, when the compression processing by the compression / write processing circuit 11 is completed, a signal indicating the completion is input to the channel selection control unit 3 to sequentially switch channels. . Thus, the memory 7 has
As shown in FIG. 3, signals for one field or one frame are sequentially stored.

If n in the video signal n is 9, for example, as shown in FIG. 5, an image of 1 to 9 of 3 horizontal screens × 3 vertical screens can be displayed on the display unit 10.

In the present invention, the amount of information can be greatly reduced by compressing the video signal by high-efficiency coding. In general, the amount of information is 1/50 to 1/100
Can be compressed to a degree. Since the compressed code data is written into the memory 7, the processing time for writing the data is significantly reduced. Therefore, the number of fields that can be written in the same time increases, so that a smooth moving image can be displayed.

Further, if the memory capacity is the same as that of the related art, it is possible to store the video of the number of fields or the number of frames which is the reciprocal multiple of the compression rate as compared with the related art. Therefore,
It is also possible to play back any video in the video to be displayed retroactively.

Further, in the present embodiment, as described above, the decompression / readout processing circuit 12 performs the interpolation process or the decimation process after the decompression process, and thus has the following excellent effects. That is, when, for example, one of the video signals 1 to n is selected and displayed on the display unit 10, the decompression / read processing circuit 12 does not need to thin out the signal read from the memory 7. Images can be displayed. Since the decompression / readout processing circuit 12 can perform interpolation processing or thinning processing in accordance with the number of images to be displayed on the display unit 10, the highest-quality image is displayed according to the number of images to be displayed on the display unit 10. Can be displayed.

[0021]

As described in detail above, the television receiver of the present invention comprises a tuner for receiving a broadcast signal wave and all the channels receivable by the tuner or a plurality of channels among them. A tuning control unit for controlling a tuner so as to select a channel; and a compression / writing unit for sequentially performing high-efficiency encoding compression of video signals of a plurality of channels obtained from the tuner in units of at least one field, and writing and accumulating them in a memory. A multi-picture processing circuit, which includes a read-out processing circuit and a decompression / read-out processing circuit that reads and decompresses the video signal stored in the memory and performs interpolation or decimation processing in accordance with the number of video images to be displayed on the display unit. The display can be performed by a moving image, and the past video can be reproduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the present invention.

FIG. 3 is a diagram for explaining the operation of the present invention.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a diagram showing an example of a multi-screen display.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 antenna 2 tuner 3 tuning control unit 4 IF circuit 5 Y / C separation / color demodulation circuit 7 memory 9 signal processing circuit 10 display unit 11 compression / write processing circuit 12 expansion / read processing circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 7/24 G06F 15/66 355C H04N 7/13 Z

Claims (1)

[Claims] 1. A television receiving apparatus for displaying a plurality of images on a display unit, comprising: a tuner for receiving a broadcast signal wave; and sequentially selecting all channels receivable by the tuner or a plurality of channels among them. A tuning control unit that controls the tuner to perform high-efficiency encoding compression on video signals of a plurality of channels obtained from the tuner in units of at least one field at a time, and writes and accumulates the video signals in a memory for storage. And a decompression / readout processing circuit for reading and decompressing the video signal stored in the memory and performing interpolation or thinning-out processing in accordance with the number of video images to be displayed on the display unit. A television receiver characterized by the above-mentioned.