JPH07298195A - Image information compressing/expanding device - Google Patents

Abstract

PURPOSE:To provide long-time recording or the recording of plural programs with any simple method while utilizing existent equipment such as an already designed integrated circuit. CONSTITUTION:The image signals of respective (2n-1) frames and 2nth frames, where n shows positive numbers, are successively selected by a selector 58 and stored in a memory 60 for rearrangement after the number of picture elements are reduced by half by band limiting due to LPF 50 and 52 and 2:1 subsampling due to subsampling circuits 54 and 56. The information on two screen of odd and even numbers in this memory 60 is regarded as an image for one frame and successively receives following DCT processing due to an 8X8 DCT circuit 62, the quantization of a DCT coefficient due to a data amount calculation circuit 64 and a quantizer 66, variable length coding due to a variable length coding circuit 68, and error correcting coding due to an error correcting coding circuit 70.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to image transmission, recording,
The present invention relates to an image information compression / decompression device for performing processing such as reproduction, and more specifically, to an image information compression / decompression device suitable for a digital VTR that handles programs such as long-term television programs and a plurality of programs. .

[0002]

2. Description of the Related Art In recent years, research and development of digital systems have also been carried out in VTRs with the aim of achieving multi-functionality and high performance, which are not possible with analog systems. For example, C. Yamamitsu,
etal, "AN EX-PERIMENTAL STUDY FOR A HOME-USE DIGITA
L VTR ", IEEE Trans. Consum. Electronics, Vol. CE-35,
No. 3, pp.450-457, August 1989, consumer digital VTRs record image data by compressing the amount of image information in order to reduce the recording area of the video tape and record the reproduced signal. A digital VTR is disclosed which is expanded by a certain amount to obtain original image information.

FIG. 7 shows an example of an image information compression / decompression device in a digital VTR. In the figure, (A)
Is a compression device, and (B) is a decompression device. First, the compression device of FIG. 1A will be described. An image signal supplied from an image pickup device or a TV broadcast receiving device (not shown) is
The data is input to the rearrangement memory 10. The input image signal is
The interlaced scanning signal is a digital signal obtained by sampling an analog image signal at a predetermined sampling frequency fs1. The rearrangement memory 10 stores an image signal for one frame consisting of two fields.

For example, when the image signal is an NTSC system signal, the image of the signal stored in the rearrangement memory 10 corresponds to 720 horizontal pixels × 480 vertical pixels. The stored image signal is sequentially read for each block of horizontal 8 pixels × vertical 8 pixels, and is supplied to the next 8 × 8 DCT circuit 12. The 8 × 8 DCT circuit 12 is a two-dimensional DCT (Discrete Cosine Tran) for a block of horizontal 8 pixels × vertical 8 pixels.
sformation: Discrete cosine transform) is a circuit for executing.

The transform coefficients obtained as a result of executing the DCT are supplied to the data amount calculation circuit 14 and the quantizer 16 in the next stage, respectively. The data amount calculation circuit 14 calculates the code amount when the transform coefficient is quantized and variable-length coded, and the quantization step is determined so that this becomes a predetermined value. The quantizer 16 quantizes the DCT transform coefficient based on the quantization step obtained by the data amount calculation circuit 14.

At this time, the unit for keeping the code amount constant is 8
Not a DCT block unit of × 8 pixels, but a unit in which a plurality of DCT blocks are collected, and one DCT block
Better quantization is achieved by collecting from the screen as far away as possible.

The output of the quantizer 16 is variable length coded by the variable length coding circuit 18 in the next stage, and further error-correction coded by the error correction coding circuit 20 in the next stage. The encoded signal is added to the coded signal by the signal adding circuit 22 to form a recording signal, which is recorded on a video tape (not shown). At this time, as disclosed in Takakura et al., "Study on variable-speed playback image quality of digital VCR", Proceedings of Annual Conference of the 1992 Television Society, 4-15, DCT blocks at adjacent positions on the screen are displayed. Continuous recording of information on the tracks of a videotape provides a variable-speed playback image that is easy to see.

Next, the decompression device will be described with reference to FIG. 1B. The reproduction signal read from the video tape is first subjected to error correction decoding by the error correction decoding circuit 24, and is further changed. The long decoding circuit 26 decodes the variable length code. The decoded signal is dequantized by the dequantizer 28 and then input to the 8 × 8 inverse DCT circuit 30. The 8 × 8 inverse DCT circuit is a circuit for executing a two-dimensional inverse DCT having 8 horizontal pixels × 8 vertical pixels.

When inverse DCT is performed on the DCT coefficient obtained by the inverse quantization, it is an image signal of horizontal 8 pixels × vertical 8 pixels, and a predetermined address (address) of the rearrangement memory 32.
Stored in. When this operation is sequentially performed and the reproduced image signal for one frame is stored in the rearrangement memory 32, this time, the image signal is read out in the horizontal direction and output as an image signal for interlaced scanning.

[0010]

By the way, in order to record / reproduce a program that is twice as long as a normal program, the length of the video tape must be doubled. It would be advantageous to be able to record for a long time on a video tape of the same length as in the existing VTR. Moreover, it is considered that the number of television channels will increase with the spread of CATV and the like in the future. From this point of view, if you can record programs on multiple channels at the same time,
Very convenient.

However, in order to achieve these, it is very troublesome to change the device configuration of the background art described above, which is disadvantageous in terms of cost. Since the compression device and the decompression device shown as the background art are made into an LSI and mass-produced for consumer use at a low cost, it is convenient if the number of changes in the compression device and the decompression device can be minimized.

The present invention focuses on these points, and realizes a long-time recording and recording of a plurality of programs by a simple method using an existing one such as an already designed integrated circuit. , That is the purpose.

[0013]

In order to achieve the above-mentioned object, in the image information compression apparatus of the present invention, the number of pixels for each frame of the image of n frames is reduced by n reducing means. (Pixel information) is reduced to about 1 / n, and the image information of these n screens is regarded as one frame image and compressed by the compression means.

Further, the number of pixels (pixel information) is reduced to approximately 1 / m for each frame for the images of the m programs by the m reduction means, and the image information of these m screens is reduced. Is regarded as one frame image and is compressed by the compression means. When the image information of a plurality of screens is regarded as one frame, the reduced image information is divided into a plurality of compression unit blocks configured by adjacent pixels in the same screen, and these compression unit blocks are compressed by the compression unit. The information is selected by the selecting means and stored in the memory means so that the information is arranged continuously and evenly on the deemed frame in the means.

In the image information decompression device of the present invention, the compressed information is decompressed by the decompression means by regarding the compressed images of a plurality of screens as one frame image, and then by the distribution means. Will be distributed to. The above and other objects, features and advantages of the present invention will be apparent from the following detailed description and the accompanying drawings.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Although there may be many embodiments of the image information compression / expansion apparatus of the present invention, an appropriate number of embodiments will be shown and described in detail here.

<First Embodiment> FIG. 1 shows the arrangement of an image information compression apparatus according to the first embodiment. In the figure, among digital image signals output from various image devices such as an image pickup device, a TV broadcast receiving device, and a VTR (not shown), odd-numbered frame image signals are supplied to the LPF 50 and even-numbered frame image signals are supplied to the LPF 52. Has been done.

The output sides of the LPFs 50 and 52 are connected to the 2: 1 sub-sampling circuits 54 and 56, and the output sides of these sub-sampling circuits 54 and 56 are the selector 5.
8 is connected. The selector 58 is for selecting the input sub-sampling signal, and its output side is connected to the rearrangement memory 60. Sorting memory 6
The output side of 0 is connected to the 8 × 8 DCT circuit 62,
The output side of this circuit is connected to the data amount calculation circuit 64 and the quantizer 66. The output side of the quantizer 66 is connected to the variable length coding circuit 68, and the output side of this circuit is connected to the error correction coding circuit 70. The output side of the error correction coding circuit 70 is connected to the signal addition circuit 72.

Of these, the LPFs 50 and 52 are filters for limiting the frequency band in the vertical or horizontal direction of the screen corresponding to the sub-sampling in the subsequent stage. The sub-sampling circuits 54 and 56 are circuits for sub-sampling the input signal at a ratio of 2: 1. The sub-sampling may be performed in the horizontal direction or the vertical direction similarly to the band limitation.

FIG. 2 shows the state of subsampling. When black circles or white circles are taken out from the image of one frame as shown in FIG. 9A, a 2: 1 sub-sampled image in the vertical direction is obtained. When a black circle or a white circle pixel is taken out as shown in FIG.
One subsampled image. As shown in FIG. 6C, when pixels of black circles or white circles are taken out, a 2: 1 sub-sampled image in the horizontal and vertical directions is obtained.

The selector 58 is a circuit for selecting and outputting the input image signal so that it is at a predetermined position on the rearrangement memory 60. The rearrangement memory 60 is a memory for storing sub-sampled image signals of two frames, an odd frame and an even frame.

FIG. 3 shows a concrete arrangement example of the image signals in the rearrangement memory 60. In FIG. 4A, sub-sampled odd frames are shown, and blocks 1 to 16 of 8 × 8 pixels are shown. FIG. 1B shows even-numbered subsampled frames, and blocks 17 to 3 of 8 × 8 pixels.
2 is shown. These blocks 1 to 32 are stored in the rearrangement memory 60, for example, as shown in FIG. Note that FIG. 3 is a simplified illustration, and the actual number of blocks is very large. 8 × 8 DCT circuit 62
The circuit from the signal adding circuit 72 to the signal adding circuit 72 is the same as the background art.

Next, the operation of the first embodiment will be described. The image signal of the odd-numbered frame is sub-sampled 2: 1 by the sub-sampling circuit 54 after band limitation by the LPF 50 (see FIG. 2). The image signal whose number of pixels has been halved by sub-sampling is selected by the selector 58.
And is stored in the sorting memory 60.

Next, the image signals of the even-numbered frames are similarly band-limited by the LPF 52 and then sub-sampled 2: 1 by the sub-sampling circuit 56. The image signal whose number of pixels has been halved by sub-sampling is selected by the selector 58 and stored in a place different from the place where the image signal of the odd-numbered frame is stored in the rearrangement memory 60. It

As a result, the image signal which is sub-sampled 2: 1 from odd and even 2 frames to be one frame in total is stored in the rearrangement memory 60 (see FIG. 3). . This stored image signal is
The data is sequentially read out for each block of horizontal 8 pixels × vertical 8 pixels and supplied to the next 8 × 8 DCT circuit 62.

The subsequent operation is similar to that of the background art. That is, in the 8 × 8 DCT circuit 62, the image signal stored in the rearrangement memory 60 is regarded as one frame, and the two-dimensional DCT is performed on the block of horizontal 8 pixels × vertical 8 pixels. The transform coefficient obtained by executing the DCT is the data amount calculation circuit 64 and the quantizer 66 in the next stage.
Is supplied to each. The data amount calculation circuit 64 calculates the code amount when the transform coefficient is quantized and variable-length coded, and the quantization step is determined so that this becomes a predetermined value.

In the quantizer 66, the data amount calculation circuit 64
The DCT transform coefficient is quantized on the basis of the quantization step obtained in. The output of the quantizer 66 is variable-length coded by the variable-length coding circuit 68 at the next stage, and further error-correction coded by the error-correction coding circuit 70 at the next stage. The coded signal is added with the code of the synchronizing signal by the signal adding circuit 72 to be a recording signal, which is recorded on a video tape (not shown).

As described above, according to the first embodiment, the LPF 5
By adding a circuit from 0, 52 to the selector 58 to the background art, the image signal is sub-sampled at a ratio of 2: 1, and a compression process such as DCT is performed on this. That is,
The information after sub-sampling has the same amount of information as that of the background art even though it is two frames of the input image, and the amount of information of the recording signal per one frame of the image is almost half that of the background art. ing. Therefore, if the signal recording density on the video tape is set to be the same as that of the background art, it is possible to record the signal of the same program with half the length of the background art, and as a result, the signal of double time is recorded on the same video tape. It is possible to record. Specifically, the signal may be recorded by a method such that the traveling speed of the video tape is set to 1/2 of the background art and the recording head is driven only once of scanning the video tape twice. .

In the first embodiment, half the data amount of information is processed in the same time as the background art. Therefore, the operation of each circuit after the sorting memory 60 is
It is also possible to perform at half the speed of the background art.

Next, the image information expansion device of the first embodiment will be described. The structure is shown in FIG. In the figure, a reproduction signal read from a video tape (not shown) is input to the error correction decoding circuit 80.
This output side is connected to the variable length decoding circuit 82,
The output side of the variable length decoding circuit 82 is connected to the inverse quantizer 84. The output side of the inverse quantizer 84 is an 8 × 8 inverse DCT
It is connected to the circuit 86, and the output side of this circuit is connected to the sorting memory 88. Sorting memory 8
The output side of 8 is connected to the distributor 90.
The output side of is connected to the 1: 2 0-value interpolation circuits 92 and 94. The output side of these 0-value interpolation circuits 92 and 94 is L
They are connected to the PFs 96 and 98, respectively.

Of these, the circuits from the error correction decoding circuit 80 to the rearrangement memory 88 are the same as in the background art. Of the image signals stored in the rearrangement memory 88, the distributor 90 outputs the odd-numbered frame signals to the zero-value interpolation circuit 92 and the even-numbered frame signals to the zero-value interpolation circuit 94.
And a circuit for distributing and outputting each. The 0-value interpolation circuits 92 and 94 are circuits for interpolating the value of “0” at a ratio of 1: 2 with respect to the input image signal. LPF
Reference numerals 96 and 98 denote circuits for limiting the frequency band of the input image signal in correspondence with the 0-value interpolation in the preceding stage. The 0-value interpolation circuits 92 and 94 and the LPFs 96 and 98 function to restore the sub-sampled image signal to the original sampling rate during compression.

Next, the operation of the image information decompression device of the first embodiment will be described. The reproduced signal read from the video tape is decoded by the error correction decoding circuit 80 as in the background art. Processing, variable length decoding circuit 82
Decoding processing of a variable length code by the above, dequantization by the dequantizer 84, and inverse DCT processing by the 8 × 8 inverse DCT circuit 86 are sequentially performed. Then, the processed image signals are stored in the rearrangement memory 88.

The image signals read out from the rearrangement memory 88 are distributed by the distributor 90 in correspondence with the image signals of the odd-numbered frames and the image signals of the even-numbered frames at the time of recording, and each has a 0 value. Interpolation circuit 92,
94. 1: 2 in the 0-value interpolation circuits 92 and 94
The value of 0 is interpolated at the ratio of
6,98 band-limited. As a result, the image signal expanded to the original sampling rate before compression is obtained for every odd and even frame. These image signals are supplied to a display means such as a CRT and the image is reproduced and displayed.

In this image information decompression device as well,
Similar to the compression side, the data of about 1/2 the amount of information is processed in the same time as the background art. Therefore, the operation of each circuit before the sorting memory 88 can be performed at half the speed of the background art.

As described above, according to the first embodiment, the image of two frames obtained by sub-sampling the image signal at 2: 1 is regarded as the image of one frame, and this is the object of the compression / expansion process. . Therefore, on the compression side, the LPF 50, 51, the sub-sampling circuit 54,
Only by adding 56 and the selector 58, a long-time program of double length can be recorded on the same video tape as the background art. On the decompression side, the distributor 90, the 0-value interpolation circuit 9
2,94, and LPF96,98 only add 2
Double-length long programs can be played from the same video tape as the background technology.

<Second Embodiment> Next, a second embodiment will be described with reference to FIG. In the second embodiment, two television programs are simultaneously recorded or reproduced. FIG. 5 shows the configuration of the image information compression apparatus according to the second embodiment. As shown in the figure, the configuration is almost the same as that of the image information compression apparatus of the first embodiment, but the LPF 50
Is supplied with the image signal of the program A, and the LPF 52 is supplied with the image signal of the program B.

A synchronization delay memory 100 is connected to the output side of the sub-sampling circuit 56, and its output side is connected to the selector 58. The synchronization delay memory 100 is a memory that performs delay processing to synchronize the image signal of the program A and the image signal of the program B.

Next, the operation of the image information compression apparatus of the second embodiment will be described. The image signal of the program A is band-limited by the LPF 50 and then 2: 1 by the sub-sampling circuit 54.
Is subsampled. The image signal of the program B is sub-sampled 2: 1 by the sub-sampling circuit 56 after the band is limited by the LPF 52. Then, the sub-sampled image signals of the programs A and B are synchronously supplied to the selector 58 by the delay processing by the synchronization delay memory 100.

In the selector 58, the input signal is selected and supplied to the sorting memory 60, and the sorting memory 60 is selected.
Stored in. As for the storage state in the rearrangement memory 60, the DCT block of the image signal of the program A is shown in FIG.
If (B) is the DCT block of the image signal of program B,
It becomes as shown in FIG. The stored image signal is horizontal 8
The blocks are sequentially read out for each block of 8 pixels by 8 pixels and supplied to the 8 × 8 DCT circuit 62 in the next stage. The subsequent operation is the same as that of the first embodiment.

As described above, according to the second embodiment, the LPF 5
By adding a circuit from 0, 52 to the selector 58 to the background art, the image signals of the programs A and B are sub-sampled at 2: 1. The image signal whose number of pixels is halved is synchronously stored in the rearrangement memory 60, and then compressed.

Therefore, the program A for the video tape,
The amount of recorded information for each B is also half that of the background art. Therefore, if the signal recording density on the video tape is the same as that of the background art, it is possible to record the signals of two programs with the same length as the background art. Although the information amount per program is halved in the second embodiment, since the two programs are handled at the same time, the information amount as a whole is the same as the background art. The operation of the circuit is similar to the background art.

Next, the image information expansion device of the second embodiment is the same as that of the first embodiment and has the configuration shown in FIG. However, in the distributor 90, the image signal of the program A is distributed to the 0-value interpolation circuit 92 side, and the image signal of the program B is distributed to the 0-value interpolation circuit 94 side. Therefore, the image signal of the program A is output from the LPF 96, and the image signal of the program B is output from the LPF 98. Either one of them may be output to a display unit such as a CRT for reproduction and display, or may be output to two display units for reproduction and display. Images of both programs may be combined and displayed in one display means.

As described above, according to the second embodiment, the frame images of two programs obtained by sub-sampling the image signal at 2: 1 are regarded as one frame image, and this is used as the object of compression / expansion processing. There is. Therefore, on the compression side, the LPFs 50 and 51 and the subsampling circuit 5 are added to the background art device.
Two programs can be recorded on the same video tape only by adding 4, 56, the delay memory 100 for synchronization, and the selector 58. Further, on the decompression side, it is only necessary to add a distributor 90, 0-value interpolation circuits 92, 94, and LPFs 96, 98,
Two programs can be played from the same video tape.

On the decompression side, although the information amount per program is almost halved, since two programs are handled at the same time, the information amount as a whole is the same as in the background art.
Therefore, the operation of the circuits up to the rearrangement memory 88 is similar to the background art.

<Third Embodiment> Next, a third embodiment will be described with reference to FIG. In this embodiment, the signal storage in the rearrangement memory 60 in the first and second embodiments is devised. In the compression side of any of the above-described embodiments, the operation after the rearrangement memory 60 is the same as the background art, and the procedure for reading the DCT block of 8 × 8 pixels from the rearrangement memory 60 is the same as the background art. is there. Therefore, as such a reading procedure, the image signals are stored in the rearrangement memory 60 in consideration of the following points.

(1) 8 pixels horizontally from the rearrangement memory 60
When reading the image signal for every 8 pixels in the vertical direction, all the pixels in the 8 × 8 block are adjacent pixels of the same screen,
Storing the image signal in the memory for rearrangement improves the coding efficiency. (2) When the unit for controlling the code amount is a plurality of DCT blocks, the DC read from the rearrangement memory 60
The rearrangement memory 6 so that the T block becomes a block at the same screen or at a position as distant from the other screen as possible.
By storing in 0, the code amount of the control unit is made uniform and more appropriate quantization is possible. (3) If the adjacent DCT blocks on the same screen are stored so that they are also adjacent to each other in the rearrangement memory 60, the information of the DCT blocks located at the adjacent positions on the screen can be continuously recorded on the track of the video tape. A variable-speed reproduced image that is easy to see can be obtained.

In consideration of such a point, FIG. 6 shows sub-sampling of two frames (an odd frame and an even frame, or a program A frame and a program B frame) in the rearrangement memory 60. An embodiment is shown for storing different signals.

In the figure, (A) shows the DCT of the image signal of the odd-numbered frame after the sub-sampling or the frame of the program A.
Blocks 1-16 are shown. In (B), DCT blocks 17 to 32 of the image signal of the odd-numbered frame after the sub-sampling or the frame of the program A are shown. These blocks 1 to 32 are, as shown in FIG.
Rearrangement is performed so that the blocks in the same figure (A) are arranged in the first and third rows in the horizontal direction and the blocks in the same figure (B) are arranged in the second and third rows. Stored in the memory 60 for use. It should be noted that FIG. 6 is also simplified and shown, and the actual number of blocks is very large.

As shown in FIG. 7C, all DCT blocks read from the rearrangement memory 60 are adjacent pixels on the same screen. Also, the sorting memory 6
By reading the DCT blocks in positions 0 as far away as possible, the DCT blocks in positions as far as possible in each frame shown in FIGS. 7A and 7B can be read. Further, adjacent DCT blocks are adjacent blocks of the same frame.

As described above, according to the third embodiment, the screen with the number of pixels reduced from the original number of pixels is divided into a plurality of DCT blocks, and the pixels in each DCT block are made adjacent to each other in the same screen. , The DCT blocks are arranged in a virtual frame after sub-sampling continuously and without bias, so that coding efficiency can be improved and proper quantization can be performed, and a reproduced image during variable speed reproduction can be easily viewed. Become.

<Other Embodiments> The present invention can be variously modified based on the above disclosure, and includes, for example, the following. (1) In the above embodiments, the input and output image signals are all digital signals sampled at the same sampling frequency fs1 as in the background art, but this is a digital signal sampled at the sampling frequency fs1 / 2. Good. In this case, the above-mentioned LPF 50,
52, 96, 98, sub-sampling circuits 54, 56,
The zero value interpolation circuits 92 and 94 are not required.

(2) The first embodiment is an example of the double long-time mode. Subsampling is performed at 2: 1 in the vertical direction and 3: 2 in the horizontal direction. 3 subframes of the sampling result of subsampling with 1 and subsampling with 3: 2 in the vertical direction, subsampling with 3: 1 in the horizontal direction, and subsampling with 3: 1 in the vertical direction. If the same processing as that in the above-described embodiment is performed using the image signal of, the triple long-time mode can be realized. The number of pixels or information may be reduced to about 1 / n for other n-time long time modes such as 4 times.

(3) In the above embodiment, two television programs are handled, but one program may be one and various programs may be output from another VTR or video camera.
Further, the number of pixels or information may be reduced to about 1 / m to handle m programs. (4) The number of pixels in the DCT block or the number of pixels in one frame shown in the above embodiment may be appropriately set as necessary. (5) Further, various well-known techniques may be applied, such as obtaining an average of adjacent pixels and performing interpolation instead of 0-value interpolation. (6) In the above embodiment, the recording of the image signal in the VTR,
Although the present invention is applied to reproduction, it is also applicable to image signal transmission. The recording medium may be something other than a video tape such as a disk medium.

[0054]

As described above, the present invention has the following effects. (1) Since the image of the n screens obtained by reducing the image signal to almost 1 / n is regarded as one frame image, and this is the object of compression / expansion processing, the existing compression device Only by adding a simple circuit to the decompression device, it is possible to realize transmission, recording, and reproduction of an n-times long-time mode image.

(2) Since the images of m programs obtained by reducing the image signal to approximately 1 / m are regarded as one frame image, and this is the object of compression / expansion processing, the existing By simply adding a simple circuit to the compression device and decompression device, transmission, recording, and reproduction of the images of m programs can be realized.

(3) Further, when considering images of a plurality of screens in which the number of pixels is reduced as one frame, pixels in the compression unit block are regarded as adjacent pixels in the same screen, and each compression unit block is regarded as a frame. In this case, since they are arranged continuously and without bias, the coding efficiency can be improved, proper quantization can be performed, and the reproduced image during variable speed reproduction can be easily viewed.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an image information compression device according to a first exemplary embodiment.

FIG. 2 is a diagram showing how sub-sampling is performed.

FIG. 3 is a diagram showing a DCT block array on a rearrangement memory.

FIG. 4 is a block diagram showing a configuration of an image information expansion device according to the first exemplary embodiment.

FIG. 5 is a block diagram illustrating a configuration of an image information compression device according to a second exemplary embodiment.

FIG. 6 is a diagram showing a DCT block array in a rearrangement memory according to a third exemplary embodiment.

FIG. 7 is a block diagram showing a background art of an image information compression / decompression device.

[Explanation of symbols]

 50, 52 ... LPF 54, 56 ... Sub sampling circuit (reduction means) 58 ... Selector (selection means) 60 ... Sorting memory (memory means) 62 ... 8 × 8 DCT circuit (compression means) 64 ... Data amount calculation circuit 66 ... Quantizer 68 ... Variable length coding circuit 70 ... Error correction coding circuit 72 ... Signal addition circuit 80 ... Error correction decoding circuit 82 ... Variable length decoding circuit 84 ... Inverse quantizer 86 ... 8 × 8 inverse DCT circuit (expansion means) 88 ... Rearrangement memory (memory means) 90 ... Distributor (distribution means) 92, 94 ... 0-value interpolation circuit (interpolation means) 96, 98 ... LPF 100 ... Synchronization delay memory (synchronization means) )

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 7/24 H04N 7/13 A

Claims (4)

[Claims] 1. n reduction means for reducing the number of pixels to approximately 1 / n for each frame of n frames of image; image information output from each of these reduction means, Selecting means for sequentially and selectively outputting; memory means for storing the image information output from this selecting means; for compressing the image information stored in this memory means by regarding it as one frame image An image information compression apparatus including a compression unit. 2. An m number of reducing means for reducing the number of pixels to approximately 1 / m for each frame for images of m number of programs; between image information output respectively from these reducing means. Synchronization means for establishing synchronization; selection means for selectively outputting image information synchronized by the synchronization means; memory means for storing image information output from the selection means; An image information compression apparatus, comprising: a compression unit for performing compression processing by regarding the stored image information as one frame image. 3. The selecting unit divides the image information of each screen output from the reducing unit into a plurality of compression unit blocks configured by adjacent pixels in the same screen, and these compression unit blocks are 3. The image information compression apparatus according to claim 1, wherein the image information compression apparatus selectively outputs the image data so that the frames are continuously arranged without any bias on the deemed frames in the compression unit. 4. A decompression means for decompressing image information that has been compressed by the image information compression device according to claim 1, as an image of one frame, and decompressed by this decompression means. Memory means for storing image information; Distributing means for distributing and outputting the image information stored in this memory means for each same screen; For each screen with respect to the image information output by this distributing means An image information decompression device comprising an interpolating means for interpolating information.